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authorTristan Gingold <tgingold@free.fr>2019-06-14 18:23:07 +0200
committerTristan Gingold <tgingold@free.fr>2019-06-19 20:47:38 +0200
commitcfde49734086a65d79e8ed4bb1a242ab0c407a40 (patch)
treecb90367bcdab5163c5437028d045aed49dc2c3f6 /src
parentf6379989022c1e71017f4151392a300534d2007a (diff)
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vhdl: decouple annotations from environments.
Diffstat (limited to 'src')
-rw-r--r--src/vhdl/simulate/simul-annotations.adb67
-rw-r--r--src/vhdl/simulate/simul-annotations.ads113
-rw-r--r--src/vhdl/simulate/simul-elaboration.adb38
-rw-r--r--src/vhdl/simulate/simul-elaboration.ads1
-rw-r--r--src/vhdl/simulate/simul-environments.adb1
-rw-r--r--src/vhdl/simulate/simul-environments.ads92
-rw-r--r--src/vhdl/simulate/simul-execution.adb81
-rw-r--r--src/vhdl/simulate/simul-execution.ads1
8 files changed, 190 insertions, 204 deletions
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb
index ddc2733c8..651dc0a5c 100644
--- a/src/vhdl/simulate/simul-annotations.adb
+++ b/src/vhdl/simulate/simul-annotations.adb
@@ -18,8 +18,6 @@
with Tables;
with Simple_IO;
-with Types; use Types;
-with Mutils; use Mutils;
with Vhdl.Std_Package;
with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Utils; use Vhdl.Utils;
@@ -93,9 +91,7 @@ package body Simul.Annotations is
| Kind_Frame
| Kind_Protected
| Kind_Package
- | Kind_Bit_Type
- | Kind_Enum_Type
- | Kind_Scalar_Type
+ | Kind_Scalar_Types
| Kind_File_Type
| Kind_Extra =>
raise Internal_Error;
@@ -177,12 +173,11 @@ package body Simul.Annotations is
Res : in out String;
Off : in out Natural)
is
- Scalar_Map : constant array (Iir_Value_Scalars) of Character := "beEIF";
+ Scalar_Map : constant array (Kind_Scalar_Types) of Character := "beeEIF";
begin
case Get_Kind (Def) is
when Iir_Kinds_Scalar_Type_And_Subtype_Definition =>
- Res (Off) :=
- Scalar_Map (Get_Info (Get_Base_Type (Def)).Scalar_Mode);
+ Res (Off) := Scalar_Map (Get_Info (Get_Base_Type (Def)).Kind);
Off := Off + 1;
when Iir_Kind_Array_Type_Definition
| Iir_Kind_Array_Subtype_Definition =>
@@ -289,25 +284,24 @@ package body Simul.Annotations is
then
Info := new Sim_Info_Type'(Kind => Kind_Bit_Type,
Ref => Def,
- Scalar_Mode => Iir_Value_B1,
Width => 1);
elsif Def = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type
or else Def = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Type
then
- Info := new Sim_Info_Type'(Kind => Kind_Bit_Type,
+ Info := new Sim_Info_Type'(Kind => Kind_Log_Type,
Ref => Def,
- Scalar_Mode => Iir_Value_E8,
Width => 1);
else
Nbr_Enums := Get_Nbr_Elements
(Get_Enumeration_Literal_List (Def));
- Info := new Sim_Info_Type'
- (Kind => Kind_Enum_Type,
- Ref => Def,
- Scalar_Mode => Iir_Value_E8,
- Width => Uns32 (Clog2 (Uns64 (Nbr_Enums))));
- if Nbr_Enums > 256 then
- Info.Scalar_Mode := Iir_Value_E32;
+ if Nbr_Enums <= 256 then
+ Info := new Sim_Info_Type'(Kind => Kind_E8_Type,
+ Ref => Def,
+ Width => 0);
+ else
+ Info := new Sim_Info_Type'(Kind => Kind_E32_Type,
+ Ref => Def,
+ Width => 0);
end if;
end if;
Set_Info (Def, Info);
@@ -342,25 +336,19 @@ package body Simul.Annotations is
(Block_Info, Get_Base_Type (Def));
when Iir_Kind_Integer_Type_Definition =>
- Set_Info (Def,
- new Sim_Info_Type'(Kind => Kind_Scalar_Type,
- Ref => Def,
- Scalar_Mode => Iir_Value_I64,
- Width => 0));
+ Set_Info (Def, new Sim_Info_Type'(Kind => Kind_I64_Type,
+ Ref => Def,
+ Width => 0));
when Iir_Kind_Floating_Type_Definition =>
- Set_Info (Def,
- new Sim_Info_Type'(Kind => Kind_Scalar_Type,
- Ref => Def,
- Scalar_Mode => Iir_Value_F64,
- Width => 0));
+ Set_Info (Def, new Sim_Info_Type'(Kind => Kind_F64_Type,
+ Ref => Def,
+ Width => 0));
when Iir_Kind_Physical_Type_Definition =>
- Set_Info (Def,
- new Sim_Info_Type'(Kind => Kind_Scalar_Type,
- Ref => Def,
- Scalar_Mode => Iir_Value_I64,
- Width => 0));
+ Set_Info (Def, new Sim_Info_Type'(Kind => Kind_I64_Type,
+ Ref => Def,
+ Width => 0));
when Iir_Kind_Array_Type_Definition =>
El := Get_Element_Subtype (Def);
@@ -1245,9 +1233,7 @@ package body Simul.Annotations is
| Kind_Quantity
| Kind_PSL =>
Put_Line ("-- slot:" & Object_Slot_Type'Image (Info.Slot));
- when Kind_Scalar_Type
- | Kind_Bit_Type
- | Kind_Enum_Type
+ when Kind_Scalar_Types
| Kind_File_Type
| Kind_Extra =>
null;
@@ -1285,13 +1271,8 @@ package body Simul.Annotations is
Put_Line ("slot:" & Object_Slot_Type'Image (Info.Slot));
when Kind_Extra =>
Put_Line ("extra:" & Extra_Slot_Type'Image (Info.Extra_Slot));
- when Kind_Scalar_Type =>
- Put_Line ("scalar type: "
- & Iir_Value_Kind'Image (Info.Scalar_Mode));
- when Kind_Bit_Type =>
- Put_Line ("bit type");
- when Kind_Enum_Type =>
- Put_Line ("enum type");
+ when Kind_Scalar_Types =>
+ Put_Line ("scalar type");
when Kind_File_Type =>
Put ("file type: ");
if Info.File_Signature = null then
diff --git a/src/vhdl/simulate/simul-annotations.ads b/src/vhdl/simulate/simul-annotations.ads
index 36a158f1e..453200450 100644
--- a/src/vhdl/simulate/simul-annotations.ads
+++ b/src/vhdl/simulate/simul-annotations.ads
@@ -16,10 +16,121 @@
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
+with Types; use Types;
with Vhdl.Nodes; use Vhdl.Nodes;
-with Simul.Environments; use Simul.Environments;
package Simul.Annotations is
+ type Object_Slot_Type is new Natural;
+
+ -- This slot is not used.
+ Invalid_Object_Slot : constant Object_Slot_Type := 0;
+
+ type Block_Instance_Id is new Natural;
+ No_Block_Instance_Id : constant Block_Instance_Id := 0;
+
+ -- For Kind_Extra: a number. Kind_Extra is not used by annotations, and
+ -- is free for another pass like preelab.
+ type Extra_Slot_Type is new Natural;
+
+ -- The annotation depends on the kind of the node.
+ type Sim_Info_Kind is
+ (
+ Kind_Block, Kind_Process, Kind_Frame, Kind_Protected, Kind_Package,
+ Kind_Bit_Type, Kind_Log_Type,
+ Kind_E8_Type, Kind_E32_Type, Kind_I64_Type, Kind_F64_Type,
+ Kind_File_Type,
+ Kind_Object, Kind_Signal,
+ Kind_File,
+ Kind_Terminal, Kind_Quantity,
+ Kind_PSL,
+ Kind_Extra
+ );
+
+ subtype Kind_Scalar_Types is Sim_Info_Kind range
+ Kind_Bit_Type ..
+ --Kind_Log_Type
+ --Kind_E8_Type
+ --Kind_E32_Type
+ --Kind_I64_Type
+ Kind_F64_Type;
+
+ subtype Kind_Discrete_Types is Sim_Info_Kind range
+ Kind_Bit_Type ..
+ --Kind_Log_Type
+ --Kind_E8_Type
+ --Kind_E32_Type
+ Kind_I64_Type;
+
+ subtype Kind_Enum_Types is Sim_Info_Kind range
+ Kind_Bit_Type ..
+ --Kind_Log_Type
+ --Kind_E8_Type
+ Kind_E32_Type;
+
+ type Instance_Slot_Type is new Integer;
+ Invalid_Instance_Slot : constant Instance_Slot_Type := -1;
+
+ type Sim_Info_Type (Kind : Sim_Info_Kind);
+ type Sim_Info_Acc is access all Sim_Info_Type;
+
+ -- Annotation for an iir node in order to be able to simulate it.
+ type Sim_Info_Type (Kind: Sim_Info_Kind) is record
+ -- Redundant, to be used only for debugging.
+ Ref : Iir;
+
+ case Kind is
+ when Kind_Block
+ | Kind_Frame
+ | Kind_Protected
+ | Kind_Process
+ | Kind_Package =>
+ -- Number of objects/signals.
+ Nbr_Objects : Object_Slot_Type;
+
+ case Kind is
+ when Kind_Block =>
+ -- Slot number in the parent (for blocks).
+ Inst_Slot : Instance_Slot_Type;
+
+ -- Number of children (blocks, generate, instantiation).
+ Nbr_Instances : Instance_Slot_Type;
+
+ when Kind_Package =>
+ Pkg_Slot : Object_Slot_Type;
+ Pkg_Parent : Sim_Info_Acc;
+
+ when others =>
+ null;
+ end case;
+
+ when Kind_Object
+ | Kind_Signal
+ | Kind_File
+ | Kind_Terminal
+ | Kind_Quantity
+ | Kind_PSL =>
+ -- Block in which this object is declared in.
+ Obj_Scope : Sim_Info_Acc;
+
+ -- Variable index in the block.
+ Slot: Object_Slot_Type;
+
+ when Kind_Bit_Type
+ | Kind_Log_Type
+ | Kind_E8_Type
+ | Kind_E32_Type
+ | Kind_I64_Type
+ | Kind_F64_Type=>
+ Width : Uns32;
+
+ when Kind_File_Type =>
+ File_Signature : String_Acc;
+
+ when Kind_Extra =>
+ Extra_Slot : Extra_Slot_Type;
+ end case;
+ end record;
+
-- Decorate the tree in order to be usable with the internal simulator.
procedure Annotate (Unit : Iir_Design_Unit);
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index c879d24b1..d1c62a2a5 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -28,7 +28,6 @@ with Name_Table;
with Simul.File_Operation;
with Vhdl.Nodes_Utils; use Vhdl.Nodes_Utils;
with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
-with Simul.Annotations; use Simul.Annotations;
with Simul.Elaboration.AMS; use Simul.Elaboration.AMS;
with Areapools; use Areapools;
with Grt.Errors;
@@ -642,18 +641,18 @@ package body Simul.Elaboration is
Bounds := Execute_Bounds (Block, Decl);
Res := Bounds.Left;
when Init_Value_Any =>
- case Iir_Value_Scalars
- (Get_Info (Get_Base_Type (Decl)).Scalar_Mode)
+ case Kind_Scalar_Types (Get_Info (Get_Base_Type (Decl)).Kind)
is
- when Iir_Value_B1 =>
+ when Kind_Bit_Type =>
Res := Create_B1_Value (False);
- when Iir_Value_E8 =>
+ when Kind_E8_Type
+ | Kind_Log_Type =>
Res := Create_E8_Value (0);
- when Iir_Value_E32 =>
+ when Kind_E32_Type =>
Res := Create_E32_Value (0);
- when Iir_Value_I64 =>
+ when Kind_I64_Type =>
Res := Create_I64_Value (0);
- when Iir_Value_F64 =>
+ when Kind_F64_Type =>
Res := Create_F64_Value (0.0);
end case;
when Init_Value_Signal =>
@@ -2478,6 +2477,17 @@ package body Simul.Elaboration is
end case;
end Elaborate_Branch_Quantity_Declaration;
+ procedure Elaborate_Declaration_Type
+ (Instance : Block_Instance_Acc; Decl: Iir)
+ is
+ Ind : constant Iir := Get_Subtype_Indication (Decl);
+ begin
+ if Ind = Null_Iir or else Get_Kind (Ind) in Iir_Kinds_Denoting_Name then
+ return;
+ end if;
+ Elaborate_Subtype_Indication (Instance, Ind);
+ end Elaborate_Declaration_Type;
+
-- LRM93 §12.3.1 Elaboration of a declaration
procedure Elaborate_Declaration (Instance : Block_Instance_Acc; Decl : Iir)
is
@@ -2508,22 +2518,19 @@ package body Simul.Elaboration is
when Iir_Kind_Subtype_Declaration =>
Elaborate_Subtype_Indication (Instance, Get_Type (Decl));
when Iir_Kind_Iterator_Declaration =>
- Elaborate_Subtype_Indication_If_Anonymous
- (Instance, Get_Type (Decl));
+ Elaborate_Declaration_Type (Instance, Decl);
Val := Create_Value_For_Type
(Instance, Get_Type (Decl), Init_Value_Default);
Create_Object (Instance, Decl);
Instance.Objects (Get_Info (Decl).Slot) :=
Unshare (Val, Instance_Pool);
when Iir_Kind_Signal_Declaration =>
- Elaborate_Subtype_Indication_If_Anonymous
- (Instance, Get_Type (Decl));
+ Elaborate_Declaration_Type (Instance, Decl);
Val := Elaborate_Default_Value (Instance, Decl);
Create_Signal (Instance, Decl);
Elaborate_Signal (Instance, Decl, Val);
when Iir_Kind_Variable_Declaration =>
- Elaborate_Subtype_Indication_If_Anonymous
- (Instance, Get_Type (Decl));
+ Elaborate_Declaration_Type (Instance, Decl);
Val := Elaborate_Default_Value (Instance, Decl);
Create_Object (Instance, Decl);
Instance.Objects (Get_Info (Decl).Slot) :=
@@ -2538,8 +2545,7 @@ package body Simul.Elaboration is
then
-- Create the object (except for full declaration of a
-- deferred constant).
- Elaborate_Subtype_Indication_If_Anonymous
- (Instance, Get_Type (Decl));
+ Elaborate_Declaration_Type (Instance, Decl);
Create_Object (Instance, Decl);
end if;
-- Initialize the value (except for a deferred declaration).
diff --git a/src/vhdl/simulate/simul-elaboration.ads b/src/vhdl/simulate/simul-elaboration.ads
index 22a912596..4c26b7d28 100644
--- a/src/vhdl/simulate/simul-elaboration.ads
+++ b/src/vhdl/simulate/simul-elaboration.ads
@@ -19,6 +19,7 @@
with Tables;
with Types; use Types;
with Vhdl.Nodes; use Vhdl.Nodes;
+with Simul.Annotations; use Simul.Annotations;
with Simul.Environments; use Simul.Environments;
with Grt.Types; use Grt.Types;
diff --git a/src/vhdl/simulate/simul-environments.adb b/src/vhdl/simulate/simul-environments.adb
index b30ef101a..356383bba 100644
--- a/src/vhdl/simulate/simul-environments.adb
+++ b/src/vhdl/simulate/simul-environments.adb
@@ -19,6 +19,7 @@
with System;
with Ada.Unchecked_Conversion;
with GNAT.Debug_Utilities;
+with Types; use Types;
with Simple_IO;
with Name_Table;
with Simul.Debugger; use Simul.Debugger;
diff --git a/src/vhdl/simulate/simul-environments.ads b/src/vhdl/simulate/simul-environments.ads
index 68109eb78..30f49aae0 100644
--- a/src/vhdl/simulate/simul-environments.ads
+++ b/src/vhdl/simulate/simul-environments.ads
@@ -17,8 +17,8 @@
-- 02111-1307, USA.
with Ada.Unchecked_Deallocation;
-with Types; use Types;
with Vhdl.Nodes; use Vhdl.Nodes;
+with Simul.Annotations; use Simul.Annotations;
with Grt.Types; use Grt.Types;
with Grt.Signals; use Grt.Signals;
with Grt.Files;
@@ -208,99 +208,9 @@ package Simul.Environments is
end case;
end record;
- type Object_Slot_Type is new Natural;
-
- -- This slot is not used.
- Invalid_Object_Slot : constant Object_Slot_Type := 0;
-
- subtype Parameter_Slot_Type is Object_Slot_Type range 0 .. 2**15;
-
- type Pkg_Index_Type is new Natural;
-
- type Block_Instance_Id is new Natural;
- No_Block_Instance_Id : constant Block_Instance_Id := 0;
-
type Objects_Array is array (Object_Slot_Type range <>) of
Iir_Value_Literal_Acc;
- -- For Kind_Extra: a number. Kind_Extra is not used by annotations, and
- -- is free for another pass like preelab.
- type Extra_Slot_Type is new Natural;
-
- -- The annotation depends on the kind of the node.
- type Sim_Info_Kind is
- (
- Kind_Block, Kind_Process, Kind_Frame, Kind_Protected, Kind_Package,
- Kind_Bit_Type, Kind_Enum_Type, Kind_Scalar_Type, Kind_File_Type,
- Kind_Object, Kind_Signal,
- Kind_File,
- Kind_Terminal, Kind_Quantity,
- Kind_PSL,
- Kind_Extra
- );
-
- type Instance_Slot_Type is new Integer;
- Invalid_Instance_Slot : constant Instance_Slot_Type := -1;
-
- type Sim_Info_Type (Kind : Sim_Info_Kind);
- type Sim_Info_Acc is access all Sim_Info_Type;
-
- -- Annotation for an iir node in order to be able to simulate it.
- type Sim_Info_Type (Kind: Sim_Info_Kind) is record
- -- Redundant, to be used only for debugging.
- Ref : Iir;
-
- case Kind is
- when Kind_Block
- | Kind_Frame
- | Kind_Protected
- | Kind_Process
- | Kind_Package =>
- -- Number of objects/signals.
- Nbr_Objects : Object_Slot_Type;
-
- case Kind is
- when Kind_Block =>
- -- Slot number in the parent (for blocks).
- Inst_Slot : Instance_Slot_Type;
-
- -- Number of children (blocks, generate, instantiation).
- Nbr_Instances : Instance_Slot_Type;
-
- when Kind_Package =>
- Pkg_Slot : Object_Slot_Type;
- Pkg_Parent : Sim_Info_Acc;
-
- when others =>
- null;
- end case;
-
- when Kind_Object
- | Kind_Signal
- | Kind_File
- | Kind_Terminal
- | Kind_Quantity
- | Kind_PSL =>
- -- Block in which this object is declared in.
- Obj_Scope : Sim_Info_Acc;
-
- -- Variable index in the block.
- Slot: Object_Slot_Type;
-
- when Kind_Scalar_Type
- | Kind_Bit_Type
- | Kind_Enum_Type =>
- Scalar_Mode : Iir_Value_Kind;
- Width : Uns32;
-
- when Kind_File_Type =>
- File_Signature : String_Acc;
-
- when Kind_Extra =>
- Extra_Slot : Extra_Slot_Type;
- end case;
- end record;
-
type Block_Instance_Type (Max_Objs : Object_Slot_Type) is record
-- Flag for wait statement: true if not yet executed.
In_Wait_Flag : Boolean;
diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb
index 20b4215f5..d7391ef95 100644
--- a/src/vhdl/simulate/simul-execution.adb
+++ b/src/vhdl/simulate/simul-execution.adb
@@ -26,7 +26,6 @@ with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Std_Package;
with Vhdl.Evaluation;
with Vhdl.Utils; use Vhdl.Utils;
-with Simul.Annotations; use Simul.Annotations;
with Name_Table;
with Simul.File_Operation;
with Simul.Debugger; use Simul.Debugger;
@@ -262,15 +261,15 @@ package body Simul.Execution is
return Iir_Value_Literal_Acc
is
Base_Type : constant Iir := Get_Base_Type (Etype);
- Mode : constant Iir_Value_Kind :=
- Get_Info (Base_Type).Scalar_Mode;
+ Kind : constant Kind_Enum_Types := Get_Info (Base_Type).Kind;
begin
- case Iir_Value_Enums (Mode) is
- when Iir_Value_E8 =>
+ case Kind is
+ when Kind_E8_Type
+ | Kind_Log_Type =>
return Create_E8_Value (Ghdl_E8 (Pos));
- when Iir_Value_E32 =>
+ when Kind_E32_Type =>
return Create_E32_Value (Ghdl_E32 (Pos));
- when Iir_Value_B1 =>
+ when Kind_Bit_Type =>
return Create_B1_Value (Ghdl_B1'Val (Pos));
end case;
end Create_Enum_Value;
@@ -1775,27 +1774,15 @@ package body Simul.Execution is
Lit: Iir_Value_Literal_Acc;
El : Iir_Value_Literal_Acc;
- Element_Mode : Iir_Value_Scalars;
Pos : Nat8;
begin
- Element_Mode := Get_Info (El_Btype).Scalar_Mode;
-
Lit := Create_Array_Value (Len, 1);
for I in Lit.Val_Array.V'Range loop
-- FIXME: use literal from type ??
Pos := Str_Table.Element_String8 (Id, Pos32 (I));
- case Element_Mode is
- when Iir_Value_B1 =>
- El := Create_B1_Value (Ghdl_B1'Val (Pos));
- when Iir_Value_E8 =>
- El := Create_E8_Value (Ghdl_E8'Val (Pos));
- when Iir_Value_E32 =>
- El := Create_E32_Value (Ghdl_E32'Val (Pos));
- when others =>
- raise Internal_Error;
- end case;
+ El := Create_Enum_Value (Natural (Pos), El_Btype);
Lit.Val_Array.V (I) := El;
end loop;
@@ -3046,8 +3033,8 @@ package body Simul.Execution is
Lit_Type : constant Iir := Get_Base_Type (Get_Type (Expr));
Lit : constant Int64 := Get_Value (Expr);
begin
- case Get_Info (Lit_Type).Scalar_Mode is
- when Iir_Value_I64 =>
+ case Get_Info (Lit_Type).Kind is
+ when Kind_I64_Type =>
return Create_I64_Value (Ghdl_I64 (Lit));
when others =>
raise Internal_Error;
@@ -3058,21 +3045,8 @@ package body Simul.Execution is
return Create_F64_Value (Ghdl_F64 (Get_Fp_Value (Expr)));
when Iir_Kind_Enumeration_Literal =>
- declare
- Lit_Type : constant Iir := Get_Base_Type (Get_Type (Expr));
- Lit : constant Iir_Int32 := Get_Enum_Pos (Expr);
- begin
- case Get_Info (Lit_Type).Scalar_Mode is
- when Iir_Value_B1 =>
- return Create_B1_Value (Ghdl_B1'Val (Lit));
- when Iir_Value_E8 =>
- return Create_E8_Value (Ghdl_E8'Val (Lit));
- when Iir_Value_E32 =>
- return Create_E32_Value (Ghdl_E32 (Lit));
- when others =>
- raise Internal_Error;
- end case;
- end;
+ return Create_Enum_Value (Natural (Get_Enum_Pos (Expr)),
+ Get_Type (Expr));
when Iir_Kind_Physical_Int_Literal
| Iir_Kind_Physical_Fp_Literal
@@ -3188,18 +3162,19 @@ package body Simul.Execution is
declare
Prefix_Type: constant Iir := Get_Type (Get_Prefix (Expr));
Base_Type : constant Iir := Get_Base_Type (Prefix_Type);
- Mode : constant Iir_Value_Kind :=
- Get_Info (Base_Type).Scalar_Mode;
+ Kind : constant Kind_Discrete_Types :=
+ Get_Info (Base_Type).Kind;
begin
Res := Execute_Expression (Block, Get_Parameter (Expr));
- case Iir_Value_Discrete (Mode) is
- when Iir_Value_I64 =>
+ case Kind is
+ when Kind_I64_Type =>
null;
- when Iir_Value_E8 =>
+ when Kind_E8_Type
+ | Kind_Log_Type =>
Res := Create_E8_Value (Ghdl_E8 (Res.I64));
- when Iir_Value_E32 =>
+ when Kind_E32_Type =>
Res := Create_E32_Value (Ghdl_E32 (Res.I64));
- when Iir_Value_B1 =>
+ when Kind_Bit_Type =>
Res := Create_B1_Value (Ghdl_B1'Val (Res.I64));
end case;
Check_Constraints (Block, Res, Prefix_Type, Expr);
@@ -3211,20 +3186,21 @@ package body Simul.Execution is
N_Res: Iir_Value_Literal_Acc;
Prefix_Type: constant Iir := Get_Type (Get_Prefix (Expr));
Base_Type : constant Iir := Get_Base_Type (Prefix_Type);
- Mode : constant Iir_Value_Kind :=
- Get_Info (Base_Type).Scalar_Mode;
+ Mode : constant Kind_Discrete_Types :=
+ Get_Info (Base_Type).Kind;
begin
Res := Execute_Expression (Block, Get_Parameter (Expr));
- case Iir_Value_Discrete (Mode) is
- when Iir_Value_I64 =>
+ case Mode is
+ when Kind_I64_Type =>
null;
- when Iir_Value_B1 =>
+ when Kind_Bit_Type =>
N_Res := Create_I64_Value (Ghdl_B1'Pos (Res.B1));
Res := N_Res;
- when Iir_Value_E8 =>
+ when Kind_E8_Type
+ | Kind_Log_Type =>
N_Res := Create_I64_Value (Ghdl_I64 (Res.E8));
Res := N_Res;
- when Iir_Value_E32 =>
+ when Kind_E32_Type =>
N_Res := Create_I64_Value (Ghdl_I64 (Res.E32));
Res := N_Res;
end case;
@@ -4016,7 +3992,6 @@ package body Simul.Execution is
Def: Iir;
Expr: Iir)
is
- Base_Type : constant Iir := Get_Base_Type (Def);
High, Low: Iir_Value_Literal_Acc;
Bound : Iir_Value_Literal_Acc;
begin
@@ -4034,7 +4009,7 @@ package body Simul.Execution is
High := Bound.Left;
Low := Bound.Right;
end if;
- case Iir_Value_Scalars (Get_Info (Base_Type).Scalar_Mode) is
+ case Iir_Value_Scalars (Value.Kind) is
when Iir_Value_I64 =>
if Value.I64 in Low.I64 .. High.I64 then
return;
diff --git a/src/vhdl/simulate/simul-execution.ads b/src/vhdl/simulate/simul-execution.ads
index 8df5ed882..e121a1bc8 100644
--- a/src/vhdl/simulate/simul-execution.ads
+++ b/src/vhdl/simulate/simul-execution.ads
@@ -17,6 +17,7 @@
-- 02111-1307, USA.
with Vhdl.Nodes; use Vhdl.Nodes;
+with Simul.Annotations; use Simul.Annotations;
with Simul.Environments; use Simul.Environments;
with Simul.Elaboration; use Simul.Elaboration;
with Areapools; use Areapools;