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authorTristan Gingold <tgingold@free.fr>2019-09-05 06:40:01 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-05 06:40:01 +0200
commitd1bcab86c7bb8e6d115a9fb5e9da08cd789f34d1 (patch)
tree8394d0717beb4777a0ba2f9e2fde3725355266af /src
parent9343f9eaf79e405c7876361e9e456b796eb3ea56 (diff)
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synth-disp_vhdl: handle arrays in disp_out_converter.
Diffstat (limited to 'src')
-rw-r--r--src/synth/synth-disp_vhdl.adb20
1 files changed, 19 insertions, 1 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb
index a7829953a..f678c367f 100644
--- a/src/synth/synth-disp_vhdl.adb
+++ b/src/synth/synth-disp_vhdl.adb
@@ -266,7 +266,25 @@ package body Synth.Disp_Vhdl is
Disp_Out_Rhs (Mname, Off, W, Full);
Put_Line (");");
else
- Error_Kind ("disp_out_converter(arr)", Ptype);
+ declare
+ Bnd : Bound_Type renames Typ.Abounds.D (1);
+ El_Type : constant Node := Get_Element_Subtype (Ptype);
+ El_W : constant Width := Get_Type_Width (Typ.Arr_El);
+ Idx : Int32;
+ begin
+ for I in 0 .. Bnd.Len - 1 loop
+ case Bnd.Dir is
+ when Iir_To =>
+ Idx := Bnd.Left + Int32 (I);
+ when Iir_Downto =>
+ Idx := Bnd.Left - Int32 (I);
+ end case;
+ Disp_Out_Converter
+ (Mname,
+ Pfx & " (" & Int32'Image (Idx) & ")",
+ Off + I * El_W, El_Type, Typ.Arr_El, False);
+ end loop;
+ end;
end if;
when Iir_Kind_Record_Type_Definition =>
declare