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| author | Tristan Gingold <tgingold@free.fr> | 2020-09-28 21:49:39 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-09-28 21:49:39 +0200 |
| commit | da729b5a521ec6abcc725142b916d166a7bee1b0 (patch) | |
| tree | 44893565f68870e928ef20f47fad8ff9fe8ccf72 /src | |
| parent | 0fc5709d298031d2571185e261e4cdfb3c85102e (diff) | |
| download | ghdl-da729b5a521ec6abcc725142b916d166a7bee1b0.tar.gz ghdl-da729b5a521ec6abcc725142b916d166a7bee1b0.tar.bz2 ghdl-da729b5a521ec6abcc725142b916d166a7bee1b0.zip | |
netlists-disp_vhdl: handle null vectors for reducation operators.
Fix #1481
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 2bc1e2758..89703642f 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -1288,9 +1288,12 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= '1' when \i0 /= (\n0 downto 0 => '0') else '0';" & NL, Inst, (0 => Iw - 1)); - else + elsif Iw = 1 then Disp_Template (" \o0 <= \i0; -- reduce or" & NL, Inst); + else + Disp_Template + (" \o0 <= '0'; -- reduce or" & NL, Inst); end if; end; when Id_Red_And => @@ -1301,9 +1304,12 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= '1' when \i0 = (\n0 downto 0 => '1') else '0';" & NL, Inst, (0 => Iw - 1)); - else + elsif Iw = 1 then Disp_Template (" \o0 <= \i0; -- reduce and" & NL, Inst); + else + Disp_Template + (" \o0 <= '1'; -- reduce and" & NL, Inst); end if; end; when Id_Red_Xor => @@ -1316,9 +1322,12 @@ package body Netlists.Disp_Vhdl is Disp_Template (" xor \i0(\n0)", Inst, (0 => I)); end loop; Disp_Template (";" & NL, Inst); - else + elsif Iw = 1 then Disp_Template (" \o0 <= \i0; -- reduce xor" & NL, Inst); + else + Disp_Template + (" \o0 <= '0'; -- reduce xor" & NL, Inst); end if; end; |