diff options
author | Tristan Gingold <tgingold@free.fr> | 2021-04-28 17:37:26 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-04-28 17:37:26 +0200 |
commit | e3a82f2e6894155cc030680332f31db6f79aba28 (patch) | |
tree | 664593aa4fbb76c2f8c8a38d13d31b9335f99472 /src | |
parent | a7334f5837fcc417173254707bc8acfc84120b47 (diff) | |
download | ghdl-e3a82f2e6894155cc030680332f31db6f79aba28.tar.gz ghdl-e3a82f2e6894155cc030680332f31db6f79aba28.tar.bz2 ghdl-e3a82f2e6894155cc030680332f31db6f79aba28.zip |
synth: file renaming for decls, expr, insts and stmts.
Diffstat (limited to 'src')
-rw-r--r-- | src/synth/synth-static_oper.adb | 2 | ||||
-rw-r--r-- | src/synth/synth-vhdl_aggr.adb | 6 | ||||
-rw-r--r-- | src/synth/synth-vhdl_context.adb | 2 | ||||
-rw-r--r-- | src/synth/synth-vhdl_decls.adb (renamed from src/synth/synth-decls.adb) | 14 | ||||
-rw-r--r-- | src/synth/synth-vhdl_decls.ads (renamed from src/synth/synth-decls.ads) | 4 | ||||
-rw-r--r-- | src/synth/synth-vhdl_expr.adb (renamed from src/synth/synth-expr.adb) | 12 | ||||
-rw-r--r-- | src/synth/synth-vhdl_expr.ads (renamed from src/synth/synth-expr.ads) | 4 | ||||
-rw-r--r-- | src/synth/synth-vhdl_files.adb | 2 | ||||
-rw-r--r-- | src/synth/synth-vhdl_insts.adb (renamed from src/synth/synth-insts.adb) | 13 | ||||
-rw-r--r-- | src/synth/synth-vhdl_insts.ads (renamed from src/synth/synth-insts.ads) | 4 | ||||
-rw-r--r-- | src/synth/synth-vhdl_oper.adb | 4 | ||||
-rw-r--r-- | src/synth/synth-vhdl_stmts.adb (renamed from src/synth/synth-stmts.adb) | 21 | ||||
-rw-r--r-- | src/synth/synth-vhdl_stmts.ads (renamed from src/synth/synth-stmts.ads) | 4 | ||||
-rw-r--r-- | src/synth/synthesis.adb | 2 |
14 files changed, 49 insertions, 45 deletions
diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 5c9db02e9..2b9b5ffab 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -29,7 +29,7 @@ with Netlists; use Netlists; with Synth.Memtype; use Synth.Memtype; with Synth.Errors; use Synth.Errors; with Synth.Source; use Synth.Source; -with Synth.Expr; use Synth.Expr; +with Synth.Vhdl_Expr; use Synth.Vhdl_Expr; with Synth.Vhdl_Oper; with Synth.Ieee.Std_Logic_1164; use Synth.Ieee.Std_Logic_1164; with Synth.Ieee.Numeric_Std; use Synth.Ieee.Numeric_Std; diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb index 250ebb1aa..fe7e95058 100644 --- a/src/synth/synth-vhdl_aggr.adb +++ b/src/synth/synth-vhdl_aggr.adb @@ -28,9 +28,9 @@ with Vhdl.Utils; use Vhdl.Utils; with Synth.Memtype; use Synth.Memtype; with Synth.Errors; use Synth.Errors; -with Synth.Expr; use Synth.Expr; -with Synth.Stmts; use Synth.Stmts; -with Synth.Decls; use Synth.Decls; +with Synth.Vhdl_Expr; use Synth.Vhdl_Expr; +with Synth.Vhdl_Stmts; use Synth.Vhdl_Stmts; +with Synth.Vhdl_Decls; use Synth.Vhdl_Decls; package body Synth.Vhdl_Aggr is type Stride_Array is array (Dim_Type range <>) of Nat32; diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index 0ef9b417e..bb3d7b98c 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -26,7 +26,7 @@ with Vhdl.Utils; with Netlists.Folds; use Netlists.Folds; -with Synth.Expr; use Synth.Expr; +with Synth.Vhdl_Expr; use Synth.Vhdl_Expr; with Netlists.Locations; package body Synth.Vhdl_Context is diff --git a/src/synth/synth-decls.adb b/src/synth/synth-vhdl_decls.adb index a8f92c1f9..7507d21b0 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-vhdl_decls.adb @@ -31,14 +31,14 @@ with Vhdl.Std_Package; with Vhdl.Ieee.Std_Logic_1164; with Synth.Vhdl_Environment; use Synth.Vhdl_Environment.Env; -with Synth.Expr; use Synth.Expr; -with Synth.Stmts; +with Synth.Vhdl_Expr; use Synth.Vhdl_Expr; +with Synth.Vhdl_Stmts; with Synth.Source; use Synth.Source; with Synth.Errors; use Synth.Errors; with Synth.Vhdl_Files; with Synth.Values; use Synth.Values; -package body Synth.Decls is +package body Synth.Vhdl_Decls is procedure Create_Var_Wire (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Init : Valtyp) is @@ -962,7 +962,7 @@ package body Synth.Decls is Ctxt : constant Context_Acc := Get_Build (Syn_Inst); Atype : constant Node := Get_Declaration_Type (Decl); Off : Value_Offsets; - Dyn : Stmts.Dyn_Name; + Dyn : Vhdl_Stmts.Dyn_Name; Res : Valtyp; Obj_Typ : Type_Acc; Base : Valtyp; @@ -976,8 +976,8 @@ package body Synth.Decls is Obj_Typ := null; end if; - Stmts.Synth_Assignment_Prefix (Syn_Inst, Get_Name (Decl), - Base, Typ, Off, Dyn); + Vhdl_Stmts.Synth_Assignment_Prefix (Syn_Inst, Get_Name (Decl), + Base, Typ, Off, Dyn); pragma Assert (Dyn.Voff = No_Net); if Base.Val.Kind = Value_Net then -- Object is a net if it is not writable. Extract the @@ -1224,4 +1224,4 @@ package body Synth.Decls is Decl := Get_Chain (Decl); end loop; end Finalize_Declarations; -end Synth.Decls; +end Synth.Vhdl_Decls; diff --git a/src/synth/synth-decls.ads b/src/synth/synth-vhdl_decls.ads index d227bdbe1..fa1569430 100644 --- a/src/synth/synth-decls.ads +++ b/src/synth/synth-vhdl_decls.ads @@ -22,7 +22,7 @@ with Netlists; use Netlists; with Synth.Vhdl_Context; use Synth.Vhdl_Context; with Synth.Objtypes; use Synth.Objtypes; -package Synth.Decls is +package Synth.Vhdl_Decls is -- Return the Param_Type for ATYPE. function Type_To_Param_Type (Atype : Node) return Param_Type; @@ -76,4 +76,4 @@ package Synth.Decls is procedure Synth_Package_Instantiation (Parent_Inst : Synth_Instance_Acc; Pkg : Node); -end Synth.Decls; +end Synth.Vhdl_Decls; diff --git a/src/synth/synth-expr.adb b/src/synth/synth-vhdl_expr.adb index d05c0d089..9b2072865 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -42,8 +42,8 @@ with Netlists.Locations; with Synth.Memtype; use Synth.Memtype; with Synth.Errors; use Synth.Errors; with Synth.Vhdl_Environment; -with Synth.Decls; -with Synth.Stmts; use Synth.Stmts; +with Synth.Vhdl_Decls; +with Synth.Vhdl_Stmts; use Synth.Vhdl_Stmts; with Synth.Vhdl_Oper; use Synth.Vhdl_Oper; with Synth.Vhdl_Heap; use Synth.Vhdl_Heap; with Synth.Debugger; @@ -52,7 +52,7 @@ with Synth.Vhdl_Aggr; with Grt.Types; with Grt.To_Strings; -package body Synth.Expr is +package body Synth.Vhdl_Expr is function Synth_Name (Syn_Inst : Synth_Instance_Acc; Name : Node) return Valtyp; @@ -537,7 +537,7 @@ package body Synth.Expr is when Iir_Kind_String_Literal8 => -- TODO: the value should be computed (once) and its type -- returned. - return Synth.Decls.Synth_Subtype_Indication + return Synth.Vhdl_Decls.Synth_Subtype_Indication (Syn_Inst, Get_Type (Expr)); when others => @@ -2498,7 +2498,7 @@ package body Synth.Expr is T : Type_Acc; Acc : Heap_Index; begin - T := Synth.Decls.Synth_Subtype_Indication + T := Synth.Vhdl_Decls.Synth_Subtype_Indication (Syn_Inst, Get_Subtype_Indication (Expr)); Acc := Allocate_By_Type (T); return Create_Value_Access (Acc, Expr_Type); @@ -2569,4 +2569,4 @@ package body Synth.Expr is (Syn_Inst, Get_Base_Type (Get_Type (Expr))); return Synth_Expression_With_Type (Syn_Inst, Expr, Basetype); end Synth_Expression_With_Basetype; -end Synth.Expr; +end Synth.Vhdl_Expr; diff --git a/src/synth/synth-expr.ads b/src/synth/synth-vhdl_expr.ads index 8dac335c4..c6726732e 100644 --- a/src/synth/synth-expr.ads +++ b/src/synth/synth-vhdl_expr.ads @@ -31,7 +31,7 @@ with Synth.Objtypes; use Synth.Objtypes; with Synth.Values; use Synth.Values; with Synth.Vhdl_Context; use Synth.Vhdl_Context; -package Synth.Expr is +package Synth.Vhdl_Expr is -- Perform a subtype conversion. Check constraints. function Synth_Subtype_Conversion (Ctxt : Context_Acc; Vt : Valtyp; @@ -149,4 +149,4 @@ package Synth.Expr is Vec : in out Logvec_Array; Vec_Off : in out Uns32; Has_Zx : in out Boolean); -end Synth.Expr; +end Synth.Vhdl_Expr; diff --git a/src/synth/synth-vhdl_files.adb b/src/synth/synth-vhdl_files.adb index 180062e01..2300ff9f9 100644 --- a/src/synth/synth-vhdl_files.adb +++ b/src/synth/synth-vhdl_files.adb @@ -26,7 +26,7 @@ with Grt.Stdio; with Synth.Memtype; use Synth.Memtype; with Synth.Objtypes; use Synth.Objtypes; -with Synth.Expr; use Synth.Expr; +with Synth.Vhdl_Expr; use Synth.Vhdl_Expr; with Synth.Errors; use Synth.Errors; package body Synth.Vhdl_Files is diff --git a/src/synth/synth-insts.adb b/src/synth/synth-vhdl_insts.adb index ac37f8b0a..679b63312 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -46,15 +46,15 @@ with Synth.Memtype; use Synth.Memtype; with Synth.Objtypes; use Synth.Objtypes; with Synth.Values; use Synth.Values; with Synth.Vhdl_Environment; use Synth.Vhdl_Environment.Env; -with Synth.Stmts; use Synth.Stmts; -with Synth.Decls; use Synth.Decls; -with Synth.Expr; use Synth.Expr; +with Synth.Vhdl_Stmts; use Synth.Vhdl_Stmts; +with Synth.Vhdl_Decls; use Synth.Vhdl_Decls; +with Synth.Vhdl_Expr; use Synth.Vhdl_Expr; with Synth.Source; use Synth.Source; with Synth.Debugger; with Synth.Vhdl_Files; with Synth.Errors; -package body Synth.Insts is +package body Synth.Vhdl_Insts is Root_Instance : Synth_Instance_Acc; function Mode_To_Port_Kind (Mode : Iir_Mode) return Port_Kind is @@ -364,7 +364,8 @@ package body Synth.Insts is begin case Get_Kind (Inter_Type) is when Iir_Kind_Array_Subtype_Definition => - if Synth.Decls.Has_Element_Subtype_Indication (Inter_Type) then + if Synth.Vhdl_Decls.Has_Element_Subtype_Indication (Inter_Type) + then Copy_Object_Subtype (Syn_Inst, Get_Element_Subtype (Inter_Type), Proto_Inst); end if; @@ -1748,4 +1749,4 @@ package body Synth.Insts is Idx := Idx + 1; end loop; end Synth_All_Instances; -end Synth.Insts; +end Synth.Vhdl_Insts; diff --git a/src/synth/synth-insts.ads b/src/synth/synth-vhdl_insts.ads index f0ac690e6..980b4ca8b 100644 --- a/src/synth/synth-insts.ads +++ b/src/synth/synth-vhdl_insts.ads @@ -21,7 +21,7 @@ with Vhdl.Nodes; use Vhdl.Nodes; with Synth.Vhdl_Context; use Synth.Vhdl_Context; with Synth.Flags; use Synth.Flags; -package Synth.Insts is +package Synth.Vhdl_Insts is -- Create the declaration of the top entity. procedure Synth_Top_Entity (Global_Instance : Synth_Instance_Acc; Arch : Node; @@ -44,4 +44,4 @@ package Synth.Insts is procedure Synth_Component_Instantiation_Statement (Syn_Inst : Synth_Instance_Acc; Stmt : Node); -end Synth.Insts; +end Synth.Vhdl_Insts; diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 2c3252a83..fadd500b5 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -34,8 +34,8 @@ with Netlists.Utils; with Synth.Memtype; use Synth.Memtype; with Synth.Errors; use Synth.Errors; -with Synth.Stmts; use Synth.Stmts; -with Synth.Expr; use Synth.Expr; +with Synth.Vhdl_Stmts; use Synth.Vhdl_Stmts; +with Synth.Vhdl_Expr; use Synth.Vhdl_Expr; with Synth.Source; with Synth.Static_Oper; use Synth.Static_Oper; diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-vhdl_stmts.adb index 8f33e3421..0f2694e06 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -41,9 +41,9 @@ with PSL.NFAs; with Synth.Memtype; use Synth.Memtype; with Synth.Errors; use Synth.Errors; -with Synth.Decls; use Synth.Decls; -with Synth.Expr; use Synth.Expr; -with Synth.Insts; use Synth.Insts; +with Synth.Vhdl_Decls; use Synth.Vhdl_Decls; +with Synth.Vhdl_Expr; use Synth.Vhdl_Expr; +with Synth.Vhdl_Insts; use Synth.Vhdl_Insts; with Synth.Source; with Synth.Vhdl_Static_Proc; with Synth.Vhdl_Heap; @@ -56,7 +56,7 @@ with Netlists.Gates; use Netlists.Gates; with Netlists.Utils; use Netlists.Utils; with Netlists.Locations; use Netlists.Locations; -package body Synth.Stmts is +package body Synth.Vhdl_Stmts is procedure Synth_Sequential_Statements (C : in out Seq_Context; Stmts : Node); @@ -302,7 +302,7 @@ package body Synth.Stmts is if Is_Fully_Constrained_Type (Targ_Type) then -- If the aggregate subtype is known, just use it. - Bnd := Expr.Synth_Array_Bounds (Syn_Inst, Targ_Type, 1); + Bnd := Vhdl_Expr.Synth_Array_Bounds (Syn_Inst, Targ_Type, 1); else -- Ok, so the subtype of the aggregate is not known, in general -- because the length of an element is not known. That's with @@ -2006,7 +2006,8 @@ package body Synth.Stmts is (C.W_Ret, Build_Control_Signal (Sub_Inst, 1, Imp)); Phi_Assign_Static (C.W_Ret, Bit1); - Decls.Synth_Declarations (C.Inst, Get_Declaration_Chain (Bod), True); + Vhdl_Decls.Synth_Declarations + (C.Inst, Get_Declaration_Chain (Bod), True); if not Is_Error (C.Inst) then Synth_Sequential_Statements (C, Get_Sequential_Statement_Chain (Bod)); end if; @@ -2031,7 +2032,8 @@ package body Synth.Stmts is Pop_Phi (Subprg_Phi); - Decls.Finalize_Declarations (C.Inst, Get_Declaration_Chain (Bod), True); + Vhdl_Decls.Finalize_Declarations + (C.Inst, Get_Declaration_Chain (Bod), True); pragma Unreferenced (Infos); -- Propagate assignments. @@ -2106,7 +2108,8 @@ package body Synth.Stmts is end if; end if; - Decls.Finalize_Declarations (C.Inst, Get_Declaration_Chain (Bod), True); + Vhdl_Decls.Finalize_Declarations + (C.Inst, Get_Declaration_Chain (Bod), True); pragma Unreferenced (Infos); return Res; @@ -3850,4 +3853,4 @@ package body Synth.Stmts is Release (M, Proc_Pool); Instance_Pool := Prev_Instance_Pool; end Synth_Verification_Unit; -end Synth.Stmts; +end Synth.Vhdl_Stmts; diff --git a/src/synth/synth-stmts.ads b/src/synth/synth-vhdl_stmts.ads index 2009b1d4f..9621a7c9f 100644 --- a/src/synth/synth-stmts.ads +++ b/src/synth/synth-vhdl_stmts.ads @@ -26,7 +26,7 @@ with Synth.Values; use Synth.Values; with Synth.Vhdl_Context; use Synth.Vhdl_Context; with Synth.Vhdl_Environment; use Synth.Vhdl_Environment.Env; -package Synth.Stmts is +package Synth.Vhdl_Stmts is procedure Synth_Subprogram_Association (Subprg_Inst : Synth_Instance_Acc; Caller_Inst : Synth_Instance_Acc; Inter_Chain : Node; @@ -164,4 +164,4 @@ private S_En : Boolean; end case; end record; -end Synth.Stmts; +end Synth.Vhdl_Stmts; diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb index 6e3dabfc0..131e6ba04 100644 --- a/src/synth/synthesis.adb +++ b/src/synth/synthesis.adb @@ -20,7 +20,7 @@ with Errorout; use Errorout; with Vhdl.Errors; use Vhdl.Errors; with Synth.Objtypes; -with Synth.Insts; use Synth.Insts; +with Synth.Vhdl_Insts; use Synth.Vhdl_Insts; with Synth.Values.Debug; pragma Unreferenced (Synth.Values.Debug); |