netlists: add dyn_insert_en gate.

4 files changed, 95 insertions, 50 deletions

diff --git a/src/synth/ghdlsynth_gates.h b/src/synth/ghdlsynth_gates.h
index 8c62c5f1d..6530f300b 100644
--- a/src/synth/ghdlsynth_gates.h
+++ b/src/synth/ghdlsynth_gates.h
@@ -61,13 +61,14 @@ enum Module_Id {
    Id_Extract = 68,
    Id_Dyn_Extract = 69,
    Id_Dyn_Insert = 70,
-   Id_Memidx = 71,
-   Id_Addidx = 72,
-   Id_Memory = 73,
-   Id_Memory_Init = 74,
-   Id_Mem_Rd = 75,
-   Id_Mem_Rd_Sync = 76,
-   Id_Mem_Wr_Sync = 77,
+   Id_Dyn_Insert_En = 71,
+   Id_Memidx = 72,
+   Id_Addidx = 73,
+   Id_Memory = 74,
+   Id_Memory_Init = 75,
+   Id_Mem_Rd = 76,
+   Id_Mem_Rd_Sync = 77,
+   Id_Mem_Wr_Sync = 78,
    Id_Edge = 80,
    Id_Assert = 81,
    Id_Assume = 82,
@@ -77,14 +78,14 @@ enum Module_Id {
    Id_Anyconst = 91,
    Id_Allseq = 92,
    Id_Anyseq = 93,
-   Id_Const_UB32 = 96,
-   Id_Const_SB32 = 97,
-   Id_Const_UL32 = 98,
-   Id_Const_UB64 = 99,
-   Id_Const_UL64 = 100,
-   Id_Const_X = 101,
-   Id_Const_Z = 102,
-   Id_Const_0 = 103,
-   Id_Const_Bit = 104,
-   Id_Const_Log = 105,
+   Id_Const_UB32 = 112,
+   Id_Const_SB32 = 113,
+   Id_Const_UL32 = 114,
+   Id_Const_UB64 = 115,
+   Id_Const_UL64 = 116,
+   Id_Const_X = 117,
+   Id_Const_Z = 118,
+   Id_Const_0 = 119,
+   Id_Const_Bit = 120,
+   Id_Const_Log = 121,
 };
diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb
index d7bb2c117..a764cad1a 100644
--- a/src/synth/netlists-builders.adb
+++ b/src/synth/netlists-builders.adb
@@ -226,10 +226,10 @@ package body Netlists.Builders is
                      Typ => Param_Uns32)));
    end Create_Dyn_Extract_Module;
 
-   procedure Create_Dyn_Insert_Module (Ctxt : Context_Acc)
+   procedure Create_Dyn_Insert_Modules (Ctxt : Context_Acc)
    is
       Outputs : Port_Desc_Array (0 .. 0);
-      Inputs : Port_Desc_Array (0 .. 2);
+      Inputs : Port_Desc_Array (0 .. 3);
       Res : Module;
    begin
       Res := New_User_Module
@@ -239,12 +239,22 @@ package body Netlists.Builders is
       Outputs := (0 => Create_Output ("o"));
       Inputs := (0 => Create_Input ("v"),
                  1 => Create_Input ("d"),
-                 2 => Create_Input ("i"));
-      Set_Port_Desc (Res, Inputs, Outputs);
+                 2 => Create_Input ("i"),
+                 3 => Create_Input ("en"));
+      Set_Port_Desc (Res, Inputs (0 .. 2), Outputs);
+      Set_Param_Desc
+        (Res, (0 => (New_Sname_Artificial (Get_Identifier ("offset")),
+                     Typ => Param_Uns32)));
+
+      Res := New_User_Module
+        (Ctxt.Design, New_Sname_Artificial (Get_Identifier ("dyn_insert_en")),
+         Id_Dyn_Insert_En, 4, 1, 1);
+      Ctxt.M_Dyn_Insert_En := Res;
+      Set_Port_Desc (Res, Inputs (0 .. 3), Outputs);
       Set_Param_Desc
         (Res, (0 => (New_Sname_Artificial (Get_Identifier ("offset")),
                      Typ => Param_Uns32)));
-   end Create_Dyn_Insert_Module;
+   end Create_Dyn_Insert_Modules;
 
    procedure Create_Memidx_Module (Ctxt : Context_Acc)
    is
@@ -587,7 +597,7 @@ package body Netlists.Builders is
 
       Create_Extract_Module (Res);
       Create_Dyn_Extract_Module (Res);
-      Create_Dyn_Insert_Module (Res);
+      Create_Dyn_Insert_Modules (Res);
       Create_Memidx_Module (Res);
       Create_Addidx_Module (Res);
 
@@ -977,9 +987,10 @@ package body Netlists.Builders is
    end Build_Extend;
 
    function Build_Dyn_Insert
-     (Ctxt : Context_Acc; I : Net; V : Net; P : Net; Off : Uns32) return Net
+     (Ctxt : Context_Acc; Mem : Net; V : Net; Idx : Net; Off : Uns32)
+     return Net
    is
-      Wd : constant Width := Get_Width (I);
+      Wd : constant Width := Get_Width (Mem);
       pragma Assert (Wd /= No_Width);
       Inst : Instance;
       O : Net;
@@ -987,15 +998,37 @@ package body Netlists.Builders is
       Inst := New_Internal_Instance (Ctxt, Ctxt.M_Dyn_Insert);
       O := Get_Output (Inst, 0);
       Set_Width (O, Wd);
-      Connect (Get_Input (Inst, 0), I);
+      Connect (Get_Input (Inst, 0), Mem);
       if V /= No_Net then
          Connect (Get_Input (Inst, 1), V);
       end if;
-      Connect (Get_Input (Inst, 2), P);
+      Connect (Get_Input (Inst, 2), Idx);
       Set_Param_Uns32 (Inst, 0, Off);
       return O;
    end Build_Dyn_Insert;
 
+   function Build_Dyn_Insert_En
+     (Ctxt : Context_Acc; Mem : Net; V : Net; Idx : Net; En : Net; Off : Uns32)
+     return Net
+   is
+      Wd : constant Width := Get_Width (Mem);
+      pragma Assert (Wd /= No_Width);
+      Inst : Instance;
+      O : Net;
+   begin
+      Inst := New_Internal_Instance (Ctxt, Ctxt.M_Dyn_Insert_En);
+      O := Get_Output (Inst, 0);
+      Set_Width (O, Wd);
+      Connect (Get_Input (Inst, 0), Mem);
+      if V /= No_Net then
+         Connect (Get_Input (Inst, 1), V);
+      end if;
+      Connect (Get_Input (Inst, 2), Idx);
+      Connect (Get_Input (Inst, 3), En);
+      Set_Param_Uns32 (Inst, 0, Off);
+      return O;
+   end Build_Dyn_Insert_En;
+
    function Build_Memidx
      (Ctxt : Context_Acc;
       I : Net; Step : Uns32; Max : Uns32; W : Width) return Net
@@ -1288,9 +1321,10 @@ package body Netlists.Builders is
    end Build_Extract;
 
    function Build_Dyn_Extract
-     (Ctxt : Context_Acc; I : Net; P : Net; Off : Uns32; W : Width) return Net
+     (Ctxt : Context_Acc; Mem : Net; Idx : Net; Off : Uns32; W : Width)
+     return Net
    is
-      Wd : constant Width := Get_Width (I);
+      Wd : constant Width := Get_Width (Mem);
       pragma Assert (Wd /= No_Width);
       pragma Assert (W > 0);
       Inst : Instance;
@@ -1299,8 +1333,8 @@ package body Netlists.Builders is
       Inst := New_Internal_Instance (Ctxt, Ctxt.M_Dyn_Extract);
       O := Get_Output (Inst, 0);
       Set_Width (O, W);
-      Connect (Get_Input (Inst, 0), I);
-      Connect (Get_Input (Inst, 1), P);
+      Connect (Get_Input (Inst, 0), Mem);
+      Connect (Get_Input (Inst, 1), Idx);
       Set_Param_Uns32 (Inst, 0, Off);
       return O;
    end Build_Dyn_Extract;
diff --git a/src/synth/netlists-builders.ads b/src/synth/netlists-builders.ads
index 4a761738b..9e97abeac 100644
--- a/src/synth/netlists-builders.ads
+++ b/src/synth/netlists-builders.ads
@@ -114,10 +114,15 @@ package Netlists.Builders is
    function Build_Extract_Bit
      (Ctxt : Context_Acc; I : Net; Off : Width) return Net;
    function Build_Dyn_Extract
-     (Ctxt : Context_Acc; I : Net; P : Net; Off : Uns32; W : Width) return Net;
+     (Ctxt : Context_Acc; Mem : Net; Idx : Net; Off : Uns32; W : Width)
+     return Net;
 
    function Build_Dyn_Insert
-     (Ctxt : Context_Acc; I : Net; V : Net; P : Net; Off : Uns32) return Net;
+     (Ctxt : Context_Acc; Mem : Net; V : Net; Idx : Net; Off : Uns32)
+     return Net;
+   function Build_Dyn_Insert_En
+     (Ctxt : Context_Acc; Mem : Net; V : Net; Idx : Net; En : Net; Off : Uns32)
+     return Net;
 
    function Build_Memidx
      (Ctxt : Context_Acc;
@@ -213,6 +218,7 @@ private
       M_Extract : Module;
       M_Dyn_Extract : Module;
       M_Dyn_Insert : Module;
+      M_Dyn_Insert_En : Module;
       M_Memidx : Module;
       M_Addidx : Module;
       M_Memory : Module;
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads
index 9458cf796..53c6ad92d 100644
--- a/src/synth/netlists-gates.ads
+++ b/src/synth/netlists-gates.ads
@@ -156,11 +156,15 @@ package Netlists.Gates is
    --  OUT := T
    Id_Dyn_Insert : constant Module_Id := 70;
 
+   --  Like Dyn_Insert but with an enable input.
+   --  Input3: enable
+   Id_Dyn_Insert_En : constant Module_Id := 71;
+
    --  OUT := IN0 * STEP,  IN0 < MAX
-   Id_Memidx : constant Module_Id := 71;
+   Id_Memidx : constant Module_Id := 72;
 
    --  OUT := IN0 + IN1, size extension.
-   Id_Addidx : constant Module_Id := 72;
+   Id_Addidx : constant Module_Id := 73;
 
    --  Represent a memory with a fixed size.
    --  This is not a regular gate as it has only one output, PORTS.
@@ -169,18 +173,18 @@ package Netlists.Gates is
    --  one connection.  The order is important as it defines the order of
    --  actions.
    --  Outputs: PORTS
-   Id_Memory : constant Module_Id := 73;
+   Id_Memory : constant Module_Id := 74;
 
    --  Same as Id_Memory but with an initial value.
    --  Input: INIT
-   Id_Memory_Init : constant Module_Id := 74;
+   Id_Memory_Init : constant Module_Id := 75;
 
    --  Asynchronous memory read port.
    --  Inputs:  PPORT  (previous memory port)
    --           ADDR
    --  Outputs: NPORT  (next memory port)
    --           DATA
-   Id_Mem_Rd : constant Module_Id := 75;
+   Id_Mem_Rd : constant Module_Id := 76;
 
    --  Synchronous memory read port.
    --  Inputs:  PPORT (previous memory port)
@@ -188,7 +192,7 @@ package Netlists.Gates is
    --           CLK
    --  Outputs: NPORT (next memory port)
    --           DATA
-   Id_Mem_Rd_Sync : constant Module_Id := 76;
+   Id_Mem_Rd_Sync : constant Module_Id := 77;
 
    --  Synchronous memory write port
    --  Inputs:  PPORT (previous memory port)
@@ -197,7 +201,7 @@ package Netlists.Gates is
    --           EN
    --           DATA
    --  Outputs: NPORT (next memory port)
-   Id_Mem_Wr_Sync : constant Module_Id := 77;
+   Id_Mem_Wr_Sync : constant Module_Id := 78;
 
    --  Positive/rising edge detector.  This is a pseudo gate.
    --  A negative edge detector can be made using by negating the clock before
@@ -224,14 +228,14 @@ package Netlists.Gates is
    --  Constants are gates with only one constant output.  There are multiple
    --  kind of constant gates: for small width, the value is stored as a
    --  parameter, possibly signed or unsigned extended.
-   Id_Const_UB32 : constant Module_Id := 96;
-   Id_Const_SB32 : constant Module_Id := 97;
-   Id_Const_UL32 : constant Module_Id := 98;
-   Id_Const_UB64 : constant Module_Id := 99;
-   Id_Const_UL64 : constant Module_Id := 100;
-   Id_Const_X : constant Module_Id := 101;
-   Id_Const_Z : constant Module_Id := 102;
-   Id_Const_0 : constant Module_Id := 103;
+   Id_Const_UB32 : constant Module_Id := 112;
+   Id_Const_SB32 : constant Module_Id := 113;
+   Id_Const_UL32 : constant Module_Id := 114;
+   Id_Const_UB64 : constant Module_Id := 115;
+   Id_Const_UL64 : constant Module_Id := 116;
+   Id_Const_X : constant Module_Id := 117;
+   Id_Const_Z : constant Module_Id := 118;
+   Id_Const_0 : constant Module_Id := 119;
 
    --  Should we keep them ?
    pragma Unreferenced (Id_Const_UB64, Id_Const_UL64);
@@ -240,8 +244,8 @@ package Netlists.Gates is
    --  For Const_Bit: param N is for bits 32*N .. 32*N+31
    --  For Const_Log: param 2*N   is for 0/1 of bits 32*N .. 32*N+31
    --                 param 2*N+1 is for Z/X of bits 32*N .. 32*N+31
-   Id_Const_Bit : constant Module_Id := 104;
-   Id_Const_Log : constant Module_Id := 105;
+   Id_Const_Bit : constant Module_Id := 120;
+   Id_Const_Log : constant Module_Id := 121;
 
    subtype Constant_Module_Id is Module_Id range Id_Const_UB32 .. Id_Const_Log;