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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-24 19:30:22 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-25 11:43:27 +0200 |
| commit | ea0d1d7dbf62673776ee594646e5ea0f1f34323e (patch) | |
| tree | fa4e3ecd5e8a4628ee0b7e6e44c271f3691e22a1 /src | |
| parent | 6336067d026a13e836b7a226961811fc8b0832e0 (diff) | |
| download | ghdl-ea0d1d7dbf62673776ee594646e5ea0f1f34323e.tar.gz ghdl-ea0d1d7dbf62673776ee594646e5ea0f1f34323e.tar.bz2 ghdl-ea0d1d7dbf62673776ee594646e5ea0f1f34323e.zip | |
synth: handle attribute names
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_expr.adb | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 26f1f2ef5..d0e6a6115 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -666,21 +666,23 @@ package body Synth.Vhdl_Expr is begin case Get_Kind (Name) is when Iir_Kind_Simple_Name - | Iir_Kind_Selected_Name => + | Iir_Kind_Selected_Name + | Iir_Kind_Attribute_Name => return Synth_Name (Syn_Inst, Get_Named_Entity (Name)); when Iir_Kind_Interface_Signal_Declaration - | Iir_Kind_Variable_Declaration - | Iir_Kind_Interface_Variable_Declaration - | Iir_Kind_Signal_Declaration - | Iir_Kind_Interface_Constant_Declaration - | Iir_Kind_Constant_Declaration - | Iir_Kind_Iterator_Declaration - | Iir_Kind_Free_Quantity_Declaration - | Iir_Kinds_Branch_Quantity_Declaration - | Iir_Kind_Object_Alias_Declaration - | Iir_Kind_Non_Object_Alias_Declaration - | Iir_Kind_File_Declaration - | Iir_Kind_Interface_File_Declaration => + | Iir_Kind_Variable_Declaration + | Iir_Kind_Interface_Variable_Declaration + | Iir_Kind_Signal_Declaration + | Iir_Kind_Interface_Constant_Declaration + | Iir_Kind_Constant_Declaration + | Iir_Kind_Iterator_Declaration + | Iir_Kind_Free_Quantity_Declaration + | Iir_Kinds_Branch_Quantity_Declaration + | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Non_Object_Alias_Declaration + | Iir_Kind_File_Declaration + | Iir_Kind_Interface_File_Declaration + | Iir_Kind_Attribute_Value => return Get_Value (Syn_Inst, Name); when Iir_Kind_Enumeration_Literal => declare @@ -2008,6 +2010,7 @@ package body Synth.Vhdl_Expr is end; when Iir_Kind_Simple_Name | Iir_Kind_Selected_Name + | Iir_Kind_Attribute_Name | Iir_Kind_Interface_Signal_Declaration -- For PSL. | Iir_Kind_Signal_Declaration -- For PSL. | Iir_Kind_Object_Alias_Declaration -- For PSL |