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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-27 05:38:23 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-27 05:38:23 +0200 |
| commit | ef32e0b2e0339ceabc55ef4ac6cfcef4b3933f21 (patch) | |
| tree | 547f3f885ce9262a69ccf5f6c12ab6296533d4e0 /src | |
| parent | 538876ee05630948c101b86829efc5f963ba5e36 (diff) | |
| download | ghdl-ef32e0b2e0339ceabc55ef4ac6cfcef4b3933f21.tar.gz ghdl-ef32e0b2e0339ceabc55ef4ac6cfcef4b3933f21.tar.bz2 ghdl-ef32e0b2e0339ceabc55ef4ac6cfcef4b3933f21.zip | |
synth-stmts: add a missing location. Fix #1267
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-stmts.adb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index d94095a5b..838f19270 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -2030,6 +2030,7 @@ package body Synth.Stmts is function Loop_Control_And (C : Seq_Context; L, R : Net) return Net is B1 : constant Net := Get_Inst_Bit1 (C.Inst); + Res : Net; begin -- Optimize common cases. if L = B1 then @@ -2037,7 +2038,9 @@ package body Synth.Stmts is elsif R = B1 then return L; else - return Build_Dyadic (Get_Build (C.Inst), Netlists.Gates.Id_And, L, R); + Res := Build_Dyadic (Get_Build (C.Inst), Netlists.Gates.Id_And, L, R); + Set_Location (Res, C.Cur_Loop.Loop_Stmt); + return Res; end if; end Loop_Control_And; |