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author | Tristan Gingold <tgingold@free.fr> | 2017-05-13 18:19:26 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-05-17 07:19:50 +0200 |
commit | 8d71ed4eb2e0e4fb4081ff8f5f220fdd44a741e2 (patch) | |
tree | 80f5d9d9203f95400b19445fa21262bb28575ef2 /testsuite/gna/bug073/adder.vhdl | |
parent | f664558a3cc4c97dbd7837afe34375a1e52323ba (diff) | |
download | ghdl-8d71ed4eb2e0e4fb4081ff8f5f220fdd44a741e2.tar.gz ghdl-8d71ed4eb2e0e4fb4081ff8f5f220fdd44a741e2.tar.bz2 ghdl-8d71ed4eb2e0e4fb4081ff8f5f220fdd44a741e2.zip |
Add testcase to compile doc example.
Diffstat (limited to 'testsuite/gna/bug073/adder.vhdl')
-rw-r--r-- | testsuite/gna/bug073/adder.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/gna/bug073/adder.vhdl b/testsuite/gna/bug073/adder.vhdl new file mode 100644 index 000000000..3e355607a --- /dev/null +++ b/testsuite/gna/bug073/adder.vhdl @@ -0,0 +1,14 @@ +entity adder is + -- `i0`, `i1` and the carry-in `ci` are inputs of the adder. + -- `s` is the sum output, `co` is the carry-out. + port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); +end adder; + +architecture rtl of adder is +begin + -- This full-adder architecture contains two concurrent assignment. + -- Compute the sum. + s <= i0 xor i1 xor ci; + -- Compute the carry. + co <= (i0 and i1) or (i0 and ci) or (i1 and ci); +end rtl; |