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author | Tristan Gingold <tgingold@free.fr> | 2016-07-25 18:54:51 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2016-07-30 07:03:40 +0200 |
commit | 037da0190f5334b2e2c5856f094659774dec8c7d (patch) | |
tree | 56850ff810a0a1b2421bb82b23cdca05395e632d /testsuite/gna/issue123 | |
parent | 209711413b989f05c039b6d5bd6acfb888b54b5a (diff) | |
download | ghdl-037da0190f5334b2e2c5856f094659774dec8c7d.tar.gz ghdl-037da0190f5334b2e2c5856f094659774dec8c7d.tar.bz2 ghdl-037da0190f5334b2e2c5856f094659774dec8c7d.zip |
Add testcase for issue #123
Diffstat (limited to 'testsuite/gna/issue123')
-rw-r--r-- | testsuite/gna/issue123/adder.vhdl | 63 | ||||
-rwxr-xr-x | testsuite/gna/issue123/testsuite.sh | 10 |
2 files changed, 73 insertions, 0 deletions
diff --git a/testsuite/gna/issue123/adder.vhdl b/testsuite/gna/issue123/adder.vhdl new file mode 100644 index 000000000..71cb1aa85 --- /dev/null +++ b/testsuite/gna/issue123/adder.vhdl @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ADDER is + generic( WIDTH : positive := 8 ); + port( CIN : in std_logic; + A : in std_logic_vector(WIDTH-1 downto 0); + B : in std_logic_vector(WIDTH-1 downto 0); + F : out std_logic_vector(WIDTH-1 downto 0); + COUT : out std_logic); +end entity ADDER; + +-- Ripple Carry Adder +architecture RCA of ADDER is + signal CIN0 : unsigned(0 downto 0); + signal FIN : unsigned(WIDTH downto 0); +begin + CIN0(0) <= CIN; + FIN <= resize(unsigned(A), WIDTH+1) + resize(unsigned(B), WIDTH+1) + CIN0; -- yes, I know it's not a ripple carry adder + F <= std_logic_vector(FIN(WIDTH-1 downto 0)); + COUT <= FIN(WIDTH); +end architecture RCA; + +-- Carry Select Adder +architecture CSA of ADDER is + component ADDER is + generic( WIDTH : positive ); + port( CIN : in std_logic; + A : in std_logic_vector(WIDTH-1 downto 0); + B : in std_logic_vector(WIDTH-1 downto 0); + F : out std_logic_vector(WIDTH-1 downto 0); + COUT : out std_logic); + end component ADDER; + signal F0, F1 : std_logic_vector(WIDTH-1 downto 0); + signal COUT0, COUT1 : std_logic; +begin + ADD0: ADDER generic map( WIDTH => WIDTH) + port map ( + CIN => '0' , + A => A , + B => B , + F => F0 , + COUT => COUT0 ); + ADD1: ADDER generic map( WIDTH => WIDTH) + port map ( + CIN => '1' , + A => A , + B => B , + F => F1 , + COUT => COUT1 ); + COUT <= COUT1 when CIN = '1' else COUT0; + F <= F1 when CIN = '1' else F0; +end architecture CSA; + +-- here's the configuration +configuration CSAC of ADDER is + for CSA + for all: ADDER + use entity work.ADDER(RCA); + end for; + end for; +end configuration CSAC; diff --git a/testsuite/gna/issue123/testsuite.sh b/testsuite/gna/issue123/testsuite.sh new file mode 100755 index 000000000..7ae990046 --- /dev/null +++ b/testsuite/gna/issue123/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze adder.vhdl +elab_simulate csac + +clean + +echo "Test successful" |