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author | tmeissner <programming@goodcleanfun.de> | 2020-05-08 11:17:48 +0200 |
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committer | tgingold <tgingold@users.noreply.github.com> | 2020-05-08 17:52:51 +0200 |
commit | 423a2dbb9716dd91307d17109fbc53ce24ddf4e3 (patch) | |
tree | cde82938a3d3e67ab9574c87e1dbb81f824df5db /testsuite/gna/issue1288 | |
parent | e2aa330a4c6a03685bd6893b4174473ce53830e8 (diff) | |
download | ghdl-423a2dbb9716dd91307d17109fbc53ce24ddf4e3.tar.gz ghdl-423a2dbb9716dd91307d17109fbc53ce24ddf4e3.tar.bz2 ghdl-423a2dbb9716dd91307d17109fbc53ce24ddf4e3.zip |
testsuite/synth, testsuite/gna: add tests for ghdl#1288
Diffstat (limited to 'testsuite/gna/issue1288')
-rw-r--r-- | testsuite/gna/issue1288/issue.vhdl | 34 | ||||
-rwxr-xr-x | testsuite/gna/issue1288/testsuite.sh | 9 |
2 files changed, 43 insertions, 0 deletions
diff --git a/testsuite/gna/issue1288/issue.vhdl b/testsuite/gna/issue1288/issue.vhdl new file mode 100644 index 000000000..23550baa4 --- /dev/null +++ b/testsuite/gna/issue1288/issue.vhdl @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity issue is +end issue; + + +architecture sim of issue is + + signal clk : std_logic := '1'; + signal a, b : std_logic := '0'; + +begin + + clk <= not clk after 5 ns; + + a <= '1' after 20 ns, + '0' after 30 ns, + '1' after 40 ns, + '0' after 50 ns; + + b <= '1' after 50 ns, + '0' after 60 ns, + '1' after 70 ns, + '0' after 80 ns; + + -- All is sensitive to rising edge of clk + -- psl default clock is rising_edge(clk); + + -- This assertion holds + -- psl NEXT_0_a : assert always (a -> next_e[3 to 5] (b)); + +end architecture sim; diff --git a/testsuite/gna/issue1288/testsuite.sh b/testsuite/gna/issue1288/testsuite.sh new file mode 100755 index 000000000..7fbb310e6 --- /dev/null +++ b/testsuite/gna/issue1288/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze -fpsl issue.vhdl + +clean + +echo "Test successful" |