testsuite/gna: complete test for #1364

3 files changed, 51 insertions, 1 deletions

diff --git a/testsuite/gna/issue1364/mwe.vhdl b/testsuite/gna/issue1364/mwe_aggr.vhdl
index 9657e98b5..9657e98b5 100644
--- a/testsuite/gna/issue1364/mwe.vhdl
+++ b/testsuite/gna/issue1364/mwe_aggr.vhdl
diff --git a/testsuite/gna/issue1364/mwe_case.vhdl b/testsuite/gna/issue1364/mwe_case.vhdl
new file mode 100644
index 000000000..5cb1f6cb4
--- /dev/null
+++ b/testsuite/gna/issue1364/mwe_case.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mwe is
+	port(
+		n_rst_i		: in std_logic;
+		clk_i     	: in std_logic	
+	);
+end entity mwe;
+
+architecture arch of mwe is
+
+signal counter 					: unsigned(2 DOWNTO 0);
+
+signal weird_clock 				: std_logic;
+signal weird_clock_parenthesis 	: std_logic;
+
+begin
+
+process(clk_i)
+begin
+	
+	-- if Reset low then weird_clock = 0
+	-- else, weird_clock is set to one for the counter = 1 or 3 or 6
+
+	if n_rst_i = '0' then
+		counter <= (others => '0');
+		weird_clock <= '0';
+		weird_clock_parenthesis <= '0';
+	elsif rising_edge(clk_i) then
+		counter <= counter+1;
+		case (counter) is
+			when "001"  => weird_clock <= '1';
+			when "011"  => weird_clock <= '1';
+			when "110"  => weird_clock <= '1';
+			when others => weird_clock <= '0';
+		end case;
+
+		case counter is
+			when "010"  => weird_clock_parenthesis <= '1';
+			when "101"  => weird_clock_parenthesis <= '1';
+			when others => weird_clock_parenthesis <= '0';
+		end case;
+		
+	end if;
+  end process;
+end;
diff --git a/testsuite/gna/issue1364/testsuite.sh b/testsuite/gna/issue1364/testsuite.sh
index 141fb1837..358efb5ab 100755
--- a/testsuite/gna/issue1364/testsuite.sh
+++ b/testsuite/gna/issue1364/testsuite.sh
@@ -2,7 +2,9 @@
 
 . ../../testenv.sh
 
-analyze_failure mwe.vhdl
+analyze_failure mwe_aggr.vhdl
+analyze -frelaxed mwe_aggr.vhdl
+analyze mwe_case.vhdl
 
 clean