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author | Tristan Gingold <tgingold@free.fr> | 2020-08-04 18:51:44 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-08-04 18:51:44 +0200 |
commit | c969350770eac2f54cf86284c5d3fd95fdcd762c (patch) | |
tree | 6e68b7375704578982192716d2fc173c3b9ed704 /testsuite/gna/issue1420 | |
parent | 75879f13fc03c1c8b3f78f1c415286ab84910e39 (diff) | |
download | ghdl-c969350770eac2f54cf86284c5d3fd95fdcd762c.tar.gz ghdl-c969350770eac2f54cf86284c5d3fd95fdcd762c.tar.bz2 ghdl-c969350770eac2f54cf86284c5d3fd95fdcd762c.zip |
testsuite/gna: add a test for #1420
Diffstat (limited to 'testsuite/gna/issue1420')
-rw-r--r-- | testsuite/gna/issue1420/ent.vhdl | 90 | ||||
-rw-r--r-- | testsuite/gna/issue1420/repro2.vhdl | 77 | ||||
-rw-r--r-- | testsuite/gna/issue1420/repro3.vhdl | 91 | ||||
-rw-r--r-- | testsuite/gna/issue1420/repro4.vhdl | 68 | ||||
-rwxr-xr-x | testsuite/gna/issue1420/testsuite.sh | 2 |
5 files changed, 328 insertions, 0 deletions
diff --git a/testsuite/gna/issue1420/ent.vhdl b/testsuite/gna/issue1420/ent.vhdl new file mode 100644 index 000000000..2bdb073fa --- /dev/null +++ b/testsuite/gna/issue1420/ent.vhdl @@ -0,0 +1,90 @@ +library ieee; +use ieee.std_logic_1164.all; +package types_pkg is + type t_av_st is record + data : std_ulogic_vector; -- src -> sink + valid : std_ulogic; -- src -> sink + empty : std_ulogic_vector; -- src -> sink + chnnl : std_ulogic_vector; -- src -> sink + end record t_av_st; + type t_arr_av_st is array (NATURAL range <>) of t_av_st; +end package types_pkg; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.numeric_std_unsigned.all; +use work.types_pkg.all; + +entity avl_st_pkt_switch is + generic( + G_SINKS : positive; + G_SOURCES : positive + ); + port( + clk : in std_ulogic; + -- Avst Sink + avst_sink : inout t_arr_av_st(G_SINKS downto 1); + avst_source : inout t_arr_av_st(G_SOURCES downto 1); + sink_sel : in std_ulogic_vector(G_SINKS downto 1); + source_sel : in std_ulogic_vector(G_SOURCES downto 1) + ); +end entity; +architecture rtl of avl_st_pkt_switch is + signal avst_current_sink : t_av_st(data(avst_sink(avst_sink'low).data'range), empty(avst_sink(avst_sink'low).empty'range), chnnl(avst_sink(avst_sink'low).chnnl'range)); +begin + + sink_sel_gen: for i in sink_sel'range generate + sink_sel_seq_proc: process(clk) is begin + avst_current_sink.valid <= '0'; + end process; + end generate; +end architecture; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.numeric_std_unsigned.all; + +use work.types_pkg.all; + +entity avl_st_pkt_switch_tb is +end entity; + +architecture tb of avl_st_pkt_switch_tb is + + constant clk_period : time := 10 ns; + signal clk : std_logic := '0'; + + constant C_VC_SOURCES : positive := 3; + constant C_VC_SINKS : positive := 3; + subtype vc_sources_range is natural range C_VC_SOURCES downto 1; + subtype vc_sinks_range is natural range C_VC_SINKS downto 1; + signal avst_snk : t_arr_av_st(vc_sinks_range)(data(8 downto 0), empty(0 downto 0), chnnl(0 downto 0)); + signal avst_src : t_arr_av_st(vc_sources_range)(data(8 downto 0), empty(0 downto 0), chnnl(0 downto 0)); + signal sink_sel : std_ulogic_vector(C_VC_SOURCES downto 1); + signal source_sel : std_ulogic_vector(C_VC_SINKS downto 1); + +begin + + main : process + begin + wait until rising_edge(clk); + end process main; + + dut_inst: entity work.avl_st_pkt_switch + generic map ( + G_SINKS => C_VC_SOURCES, + G_SOURCES => C_VC_SINKS) + port map ( + clk => clk, + avst_sink => avst_src, + avst_source => avst_snk, + sink_sel => sink_sel, + source_sel => source_sel + ); + + clk <= not clk after clk_period / 2; + +end architecture tb; diff --git a/testsuite/gna/issue1420/repro2.vhdl b/testsuite/gna/issue1420/repro2.vhdl new file mode 100644 index 000000000..a91da4e94 --- /dev/null +++ b/testsuite/gna/issue1420/repro2.vhdl @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +package repro2_pkg is + type t_av_st is record + data : std_ulogic_vector; -- src -> sink + valid : std_ulogic; -- src -> sink + empty : std_ulogic_vector; -- src -> sink + chnnl : std_ulogic_vector; -- src -> sink + end record t_av_st; + type t_arr_av_st is array (NATURAL range <>) of t_av_st; +end package repro2_pkg; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.numeric_std_unsigned.all; +use work.repro2_pkg.all; + +entity repro2_sub is + generic( + G_SINKS : positive; + G_SOURCES : positive + ); + port( + clk : in std_ulogic; + -- Avst Sink + avst_sink : inout t_arr_av_st(G_SINKS downto 1) + ); +end entity; + +architecture rtl of repro2_sub is + signal avst_current_sink : t_av_st(data(avst_sink(avst_sink'low).data'range), empty(avst_sink(avst_sink'low).empty'range), chnnl(avst_sink(avst_sink'low).chnnl'range)); +begin + +-- sink_sel_gen: for i in sink_sel'range generate +-- sink_sel_seq_proc: process(clk) is begin +-- avst_current_sink.valid <= '0'; +-- end process; +-- end generate; +end architecture; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.numeric_std_unsigned.all; + +use work.repro2_pkg.all; + +entity repro2 is +end entity; + +architecture tb of repro2 is + + constant clk_period : time := 10 ns; + signal clk : std_logic := '0'; + + constant C_VC_SOURCES : positive := 3; + constant C_VC_SINKS : positive := 3; + subtype vc_sources_range is natural range C_VC_SOURCES downto 1; + subtype vc_sinks_range is natural range C_VC_SINKS downto 1; + signal avst_src : t_arr_av_st(vc_sources_range)(data(8 downto 0), empty(0 downto 0), chnnl(0 downto 0)); + +begin + + dut_inst: entity work.repro2_sub + generic map ( + G_SINKS => C_VC_SOURCES, + G_SOURCES => C_VC_SINKS) + port map ( + clk => clk, + avst_sink => avst_src + ); + + clk <= not clk after clk_period / 2; + +end architecture tb; diff --git a/testsuite/gna/issue1420/repro3.vhdl b/testsuite/gna/issue1420/repro3.vhdl new file mode 100644 index 000000000..8c127d22e --- /dev/null +++ b/testsuite/gna/issue1420/repro3.vhdl @@ -0,0 +1,91 @@ +library ieee; +use ieee.std_logic_1164.all; +package repro3_pkg is + type t_av_st is record + data : std_ulogic_vector; -- src -> sink + valid : std_ulogic; -- src -> sink + empty : std_ulogic_vector; -- src -> sink + chnnl : std_ulogic_vector; -- src -> sink + end record t_av_st; + type t_arr_av_st is array (NATURAL range <>) of t_av_st; +end package repro3_pkg; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.numeric_std_unsigned.all; +use work.repro3_pkg.all; + +entity repro3_sub is + generic( + G_SINKS : positive; + G_SOURCES : positive + ); + port( + clk : in std_ulogic; + -- Avst Sink + avst_sink : inout t_arr_av_st(G_SINKS downto 1); + avst_source : inout t_arr_av_st(G_SOURCES downto 1); + sink_sel : in std_ulogic_vector(G_SINKS downto 1); + source_sel : in std_ulogic_vector(G_SOURCES downto 1) + ); +end entity; + +architecture rtl of repro3_sub is + signal avst_current_sink : t_av_st(data(avst_sink(avst_sink'low).data'range), empty(avst_sink(avst_sink'low).empty'range), chnnl(avst_sink(avst_sink'low).chnnl'range)); +begin + +-- sink_sel_gen: for i in sink_sel'range generate +-- sink_sel_seq_proc: process(clk) is begin +-- avst_current_sink.valid <= '0'; +-- end process; +-- end generate; +end architecture; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.numeric_std_unsigned.all; + +use work.repro3_pkg.all; + +entity repro3 is +end entity; + +architecture tb of repro3 is + + constant clk_period : time := 10 ns; + signal clk : std_logic := '0'; + + constant C_VC_SOURCES : positive := 3; + constant C_VC_SINKS : positive := 3; + subtype vc_sources_range is natural range C_VC_SOURCES downto 1; + subtype vc_sinks_range is natural range C_VC_SINKS downto 1; + signal avst_snk : t_arr_av_st(vc_sinks_range)(data(8 downto 0), empty(0 downto 0), chnnl(0 downto 0)); + signal avst_src : t_arr_av_st(vc_sources_range)(data(8 downto 0), empty(0 downto 0), chnnl(0 downto 0)); + signal sink_sel : std_ulogic_vector(C_VC_SOURCES downto 1); + signal source_sel : std_ulogic_vector(C_VC_SINKS downto 1); + +begin + + main : process + begin + wait until rising_edge(clk); + end process main; + + dut_inst: entity work.repro3_sub + generic map ( + G_SINKS => C_VC_SOURCES, + G_SOURCES => C_VC_SINKS) + port map ( + clk => clk, + avst_sink => avst_src, + avst_source => avst_snk, + sink_sel => sink_sel, + source_sel => source_sel + ); + + clk <= not clk after clk_period / 2; + +end architecture tb; diff --git a/testsuite/gna/issue1420/repro4.vhdl b/testsuite/gna/issue1420/repro4.vhdl new file mode 100644 index 000000000..2e9842eed --- /dev/null +++ b/testsuite/gna/issue1420/repro4.vhdl @@ -0,0 +1,68 @@ +library ieee; +use ieee.std_logic_1164.all; + +package repro4_pkg is + type t_av_st is record + data : std_ulogic_vector; -- src -> sink + valid : std_ulogic; -- src -> sink + empty : std_ulogic_vector; -- src -> sink + end record t_av_st; + type t_arr_av_st is array (NATURAL range <>) of t_av_st; +end package repro4_pkg; + +library ieee; +use ieee.std_logic_1164.all; +use work.repro4_pkg.all; + +entity repro4_sub is + generic( + G_SINKS : positive; + G_SOURCES : positive + ); + port( + avst_sink : inout t_arr_av_st(G_SINKS downto 1); + avst_source : inout t_arr_av_st(G_SOURCES downto 1); + source_sel : in std_ulogic_vector(G_SOURCES downto 1) + ); +end entity; + +architecture rtl of repro4_sub is +-- signal avst_current_sink : t_av_st(data(avst_sink(avst_sink'low).data'range), empty(avst_sink(avst_sink'low).empty'range)); +begin + +-- sink_sel_gen: for i in sink_sel'range generate +-- sink_sel_seq_proc: process(clk) is begin +-- avst_current_sink.valid <= '0'; +-- end process; +-- end generate; +end architecture; + + +library ieee; +use ieee.std_logic_1164.all; +use work.repro4_pkg.all; + +entity repro4 is +end entity; + +architecture tb of repro4 is + constant C_VC_SOURCES : positive := 3; + constant C_VC_SINKS : positive := 3; + + subtype vc_sources_range is natural range C_VC_SOURCES downto 1; + subtype vc_sinks_range is natural range C_VC_SINKS downto 1; + + signal avst_snk : t_arr_av_st(vc_sinks_range)(data(8 downto 0), empty(0 downto 0)); + signal avst_src : t_arr_av_st(vc_sources_range)(data(8 downto 0), empty(0 downto 0)); + signal source_sel : std_ulogic_vector(C_VC_SINKS downto 1); +begin + dut_inst: entity work.repro4_sub + generic map ( + G_SINKS => C_VC_SOURCES, + G_SOURCES => C_VC_SINKS) + port map ( + avst_sink => avst_src, + avst_source => avst_snk, + source_sel => source_sel + ); +end architecture tb; diff --git a/testsuite/gna/issue1420/testsuite.sh b/testsuite/gna/issue1420/testsuite.sh index 5cfa1ed62..8c0b8d5ac 100755 --- a/testsuite/gna/issue1420/testsuite.sh +++ b/testsuite/gna/issue1420/testsuite.sh @@ -9,6 +9,8 @@ if ghdl_has_feature repro1 dump-rti; then elab_simulate repro1 --dump-rti fi +analyze repro3.vhdl +elab_simulate repro3 --trace-signals --stop-time=0ns > /dev/null clean echo "Test successful" |