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author | Tristan Gingold <tgingold@free.fr> | 2022-06-19 16:18:08 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-06-19 16:18:08 +0200 |
commit | 7b76e036e0856d49e207e2ff5e406860868523d5 (patch) | |
tree | d3a85393d89e1863edad8f660c81c7a535827de3 /testsuite/gna/issue2066/aggregate_bug.vhdl | |
parent | 86e2642d7ee6f2932335de3766356fe4be55183d (diff) | |
download | ghdl-7b76e036e0856d49e207e2ff5e406860868523d5.tar.gz ghdl-7b76e036e0856d49e207e2ff5e406860868523d5.tar.bz2 ghdl-7b76e036e0856d49e207e2ff5e406860868523d5.zip |
testsuite/gna: add a test for #2066
Diffstat (limited to 'testsuite/gna/issue2066/aggregate_bug.vhdl')
-rw-r--r-- | testsuite/gna/issue2066/aggregate_bug.vhdl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/gna/issue2066/aggregate_bug.vhdl b/testsuite/gna/issue2066/aggregate_bug.vhdl new file mode 100644 index 000000000..bf7b53510 --- /dev/null +++ b/testsuite/gna/issue2066/aggregate_bug.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity aggregate_bug is +end entity aggregate_bug; + +architecture rtl of aggregate_bug is + signal vec : std_logic_vector(7 downto 0); +begin + vec <= (3 downto 0 => "111", others => '0'); -- Associate a 3 bit element to a 4 bit slice + process + begin + wait for 1 ns; + report to_string(vec); + wait for 1 ns; + std.env.finish; + end process; +end architecture rtl; |