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authorTristan Gingold <tgingold@free.fr>2022-06-15 19:03:19 +0200
committerTristan Gingold <tgingold@free.fr>2022-06-15 19:03:19 +0200
commita85641c47827cb10ca07ff6dee9c49bf67d5757d (patch)
tree3c302d3f91ce1fa8f2ff4d234f58a5f522de5ab4 /testsuite/gna/issue2071/repro.vhdl
parentc8af6888a2a4b2d73f759ba8663882a8c34c75a4 (diff)
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testsuite/gna: add a test for #2071
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diff --git a/testsuite/gna/issue2071/repro.vhdl b/testsuite/gna/issue2071/repro.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity repro is
+end;
+
+architecture behav of repro is
+ type matrixType is array(natural range <>) of std_logic_vector;
+ signal matrix : matrixType(0 to 15)(7 downto 0);
+
+ -- Missing feature:
+ signal row1 : unsigned(matrix'element'range);
+
+ -- As a workaround:
+ signal row2 : unsigned(matrix(matrix'low)'range);
+begin
+end behav;