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author | Tristan Gingold <tgingold@free.fr> | 2016-12-22 06:38:17 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2016-12-22 06:38:17 +0100 |
commit | a105ec0274b527162bce87285179bc08e822017f (patch) | |
tree | bf1cf97c1ec78699be9545d6289555b2e29e20da /testsuite/gna/issue244 | |
parent | 1894be584a56543cb04b0f0b21c8deeac05605ef (diff) | |
download | ghdl-a105ec0274b527162bce87285179bc08e822017f.tar.gz ghdl-a105ec0274b527162bce87285179bc08e822017f.tar.bz2 ghdl-a105ec0274b527162bce87285179bc08e822017f.zip |
Add issue #244 testcase
Diffstat (limited to 'testsuite/gna/issue244')
-rw-r--r-- | testsuite/gna/issue244/test.vhdl | 21 | ||||
-rwxr-xr-x | testsuite/gna/issue244/testsuite.sh | 11 |
2 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/gna/issue244/test.vhdl b/testsuite/gna/issue244/test.vhdl new file mode 100644 index 000000000..110da9c95 --- /dev/null +++ b/testsuite/gna/issue244/test.vhdl @@ -0,0 +1,21 @@ +entity test is +end entity test; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +architecture rtl of test is + + FUNCTION test + RETURN std_ulogic_vector IS + SUBTYPE vector_t IS std_ulogic_vector(0 TO 3); + BEGIN + RETURN vector_t'(OTHERS => '0'); + END test; + +begin + + + +end architecture rtl; diff --git a/testsuite/gna/issue244/testsuite.sh b/testsuite/gna/issue244/testsuite.sh new file mode 100755 index 000000000..75c3f3348 --- /dev/null +++ b/testsuite/gna/issue244/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS="--std=08 --ieee=synopsys" +analyze test.vhdl +elab_simulate test + +clean + +echo "Test successful" |