Testcase for incorrect use of PSL endpoint in expressions.

3 files changed, 129 insertions, 0 deletions

diff --git a/testsuite/gna/issue45/endpoint_eval.vhdl b/testsuite/gna/issue45/endpoint_eval.vhdl
new file mode 100644
index 000000000..45250c97d
--- /dev/null
+++ b/testsuite/gna/issue45/endpoint_eval.vhdl
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library std;
+use std.env.all;
+
+
+
+entity psl_endpoint_eval_in_vhdl is
+end entity psl_endpoint_eval_in_vhdl;
+
+
+
+architecture test of psl_endpoint_eval_in_vhdl is
+
+
+  signal s_rst_n : std_logic := '0';
+  signal s_clk   : std_logic := '0';
+  signal s_write : std_logic;
+  signal s_read  : std_logic;
+
+
+begin
+
+
+  s_rst_n <= '1' after 100 ns;
+  s_clk   <= not s_clk after 10 ns;
+
+
+  TestP : process is
+  begin
+    report "RUNNING psl_endpoint_eval_in_vhdl test case";
+    report "==========================================";
+    s_write <= '0';  -- named assertion should hit
+    s_read  <= '0';
+    wait until s_rst_n = '1' and rising_edge(s_clk);
+    s_write <= '1';
+    wait until rising_edge(s_clk);
+    s_read  <= '1';  -- assertion should hit
+    wait until rising_edge(s_clk);
+    s_write <= '0';
+    s_read  <= '0';
+    wait until rising_edge(s_clk);
+    stop(0);
+    wait;
+  end process TestP;
+
+
+  -- psl default clock is rising_edge(s_clk);
+  -- psl endpoint E_TEST0 is {not(s_write); s_write};
+
+
+  process is
+  begin
+    wait until E_TEST0;
+    report "HIT";
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/gna/issue45/endpoint_eval_err.vhdl b/testsuite/gna/issue45/endpoint_eval_err.vhdl
new file mode 100644
index 000000000..1964738e8
--- /dev/null
+++ b/testsuite/gna/issue45/endpoint_eval_err.vhdl
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library std;
+use std.env.all;
+
+
+
+entity psl_endpoint_eval_in_vhdl is
+end entity psl_endpoint_eval_in_vhdl;
+
+
+
+architecture test of psl_endpoint_eval_in_vhdl is
+
+
+  signal s_rst_n : std_logic := '0';
+  signal s_clk   : std_logic := '0';
+  signal s_write : std_logic;
+  signal s_read  : std_logic;
+
+
+begin
+
+
+  s_rst_n <= '1' after 100 ns;
+  s_clk   <= not s_clk after 10 ns;
+
+
+  TestP : process is
+  begin
+    report "RUNNING psl_endpoint_eval_in_vhdl test case";
+    report "==========================================";
+    s_write <= '0';  -- named assertion should hit
+    s_read  <= '0';
+    wait until s_rst_n = '1' and rising_edge(s_clk);
+    s_write <= '1';
+    wait until rising_edge(s_clk);
+    s_read  <= '1';  -- assertion should hit
+    wait until rising_edge(s_clk);
+    s_write <= '0';
+    s_read  <= '0';
+    wait until rising_edge(s_clk);
+    stop(0);
+    wait;
+  end process TestP;
+
+
+  -- psl default clock is rising_edge(s_clk);
+  -- psl endpoint E_TEST0 is {not(s_write); s_write};
+
+
+  process is
+  begin
+    wait for E_TEST0;
+    report "HIT";
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/gna/issue45/testsuite.sh b/testsuite/gna/issue45/testsuite.sh
index 79e947ecc..43e3613c1 100755
--- a/testsuite/gna/issue45/testsuite.sh
+++ b/testsuite/gna/issue45/testsuite.sh
@@ -13,6 +13,11 @@ rm psl.out
 analyze test2.vhdl
 elab_simulate psl_test2_endpoint --assert-level=error --expect-failure
 
+analyze_failure endpoint_eval_err.vhdl
+
+analyze endpoint_eval.vhdl
+elab_simulate psl_endpoint_eval_in_vhdl
+
 clean
 
 echo "Test successful"