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author | Tristan Gingold <tgingold@free.fr> | 2018-11-04 08:54:38 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-11-07 20:53:22 +0100 |
commit | 51d6cab20ab8e08d1de3a0dc922a374ad42b6421 (patch) | |
tree | f6f4b881c861e52f85d7f41382919ec7f1f59cf1 /testsuite/gna/issue687/ent4.vhdl | |
parent | 00d347e8de432216665e6cedb8b46b7ca0c87a69 (diff) | |
download | ghdl-51d6cab20ab8e08d1de3a0dc922a374ad42b6421.tar.gz ghdl-51d6cab20ab8e08d1de3a0dc922a374ad42b6421.tar.bz2 ghdl-51d6cab20ab8e08d1de3a0dc922a374ad42b6421.zip |
Add reproducer for #687
Diffstat (limited to 'testsuite/gna/issue687/ent4.vhdl')
-rw-r--r-- | testsuite/gna/issue687/ent4.vhdl | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/gna/issue687/ent4.vhdl b/testsuite/gna/issue687/ent4.vhdl new file mode 100644 index 000000000..6b3501a18 --- /dev/null +++ b/testsuite/gna/issue687/ent4.vhdl @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; +entity dut is + port ( + sig_i : in std_logic_vector; + sig_o : out std_logic_vector + ); +end entity; +architecture arch of dut is +begin + process + begin + sig_o <= sig_i; + report "not expected" severity note; + sig_o(1) <= '1' after 1 ns; + wait; + end process; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; +entity tb is +end entity; +architecture bench of tb is + signal sin : std_ulogic_vector(1 downto 0); + signal sout : std_ulogic_vector(31 downto 0); +begin + stim : process + begin + wait for 3 ns; + report to_string(sin); + report to_string(sout); + std.env.finish; + end process; + dut_inst: entity work.dut port map ( + sig_i => sin, + sig_o => sout + ); +end architecture; |