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author | Tristan Gingold <tgingold@free.fr> | 2018-11-10 07:46:16 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-11-10 07:46:16 +0100 |
commit | 3bd4d200a891ac813d60aa6bd9d055f43da972d6 (patch) | |
tree | eec9a2c6005c980fb4c02ec68a1010adf5dae5ee /testsuite/gna/issue689/example.vhdl | |
parent | b9520bab77b8c1949c25fb5ca5bb55d739c8cfda (diff) | |
download | ghdl-3bd4d200a891ac813d60aa6bd9d055f43da972d6.tar.gz ghdl-3bd4d200a891ac813d60aa6bd9d055f43da972d6.tar.bz2 ghdl-3bd4d200a891ac813d60aa6bd9d055f43da972d6.zip |
Add testcase from #689
close #689
Diffstat (limited to 'testsuite/gna/issue689/example.vhdl')
-rw-r--r-- | testsuite/gna/issue689/example.vhdl | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/testsuite/gna/issue689/example.vhdl b/testsuite/gna/issue689/example.vhdl new file mode 100644 index 000000000..6b40fa4a9 --- /dev/null +++ b/testsuite/gna/issue689/example.vhdl @@ -0,0 +1,37 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package test_pkg is + type my_array is array(natural range <>) of unsigned; +end package test_pkg; + +--library vunit_lib; +--context vunit_lib.vunit_context; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; +use work.test_pkg.all; + +entity tb_example is + generic (runner_cfg : string := "x"); +end entity; + +architecture tb of tb_example is + constant DDR_DATA_WIDTH : integer := 128; + constant FILTER_WORD_SIZE : integer := 16; + +-- signal switch_out : my_array(0 to DDR_DATA_WIDTH / FILTER_WORD_SIZE - 1)(natural(log2(real(DDR_DATA_WIDTH / FILTER_WORD_SIZE))) - 1 downto 0); + signal switch_out : my_array(0 to 7)(2 downto 0); + +begin + main : process + begin + -- test_runner_setup(runner, runner_cfg); + report "Hello world!"; + -- test_runner_cleanup(runner); -- Simulation ends here + wait; + end process; +end architecture; |