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author | Tristan Gingold <tgingold@free.fr> | 2019-07-09 05:15:27 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-09 05:15:27 +0200 |
commit | 0926686937d3c673f46cd0d5c770a7fd4744a47d (patch) | |
tree | cc4e24838e2a65555db657368a706f7ae3a8f26f /testsuite/gna/issue864/mwe2.vhdl | |
parent | f722968eeda135aeb50d287b6d83627763191323 (diff) | |
download | ghdl-0926686937d3c673f46cd0d5c770a7fd4744a47d.tar.gz ghdl-0926686937d3c673f46cd0d5c770a7fd4744a47d.tar.bz2 ghdl-0926686937d3c673f46cd0d5c770a7fd4744a47d.zip |
Add testcase for #864
Diffstat (limited to 'testsuite/gna/issue864/mwe2.vhdl')
-rw-r--r-- | testsuite/gna/issue864/mwe2.vhdl | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/testsuite/gna/issue864/mwe2.vhdl b/testsuite/gna/issue864/mwe2.vhdl new file mode 100644 index 000000000..fe6507ca5 --- /dev/null +++ b/testsuite/gna/issue864/mwe2.vhdl @@ -0,0 +1,40 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity a is + port ( + a_in : IN std_logic; + a_out : OUT std_logic + ); +end entity a; + +library ieee; +use ieee.std_logic_1164.all; + +entity b is + port ( + b_in : IN std_logic; + b_out : OUT std_logic + ); +end entity b; + +architecture rtl of a is +begin + process (a_in) + begin + a_out <= a_in; + end process; +end architecture rtl; + +architecture rtl of b is + component a + port ( + a_in : IN std_logic; + a_out : OUT std_logic + ); + end component; + + for a0 : a; +begin + a0: a port map (a_in => b_in, a_out => b_out); +end architecture rtl; |