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authorTristan Gingold <tgingold@free.fr>2013-12-18 05:53:22 +0100
committerTristan Gingold <tgingold@free.fr>2013-12-18 05:53:22 +0100
commitbd4aff0f670351c0652cf24e9b04361dc0e3a01c (patch)
treeafcc1050ac74fc64b5756e2550bc32ea61d1e7bb /testsuite/gna/sr2553/2553.vhd
parent5fde24d46fae799e6c0723850097a8fccd64d747 (diff)
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Add initial testsuite, using regression tests from bugs or support
reported on gna.org
Diffstat (limited to 'testsuite/gna/sr2553/2553.vhd')
-rw-r--r--testsuite/gna/sr2553/2553.vhd44
1 files changed, 44 insertions, 0 deletions
diff --git a/testsuite/gna/sr2553/2553.vhd b/testsuite/gna/sr2553/2553.vhd
new file mode 100644
index 000000000..858a10b98
--- /dev/null
+++ b/testsuite/gna/sr2553/2553.vhd
@@ -0,0 +1,44 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+
+entity e1 is
+
+port(
+
+r1: in real;
+
+slv1: in std_logic_vector(7 downto 0);
+
+sl1: in std_logic
+
+);
+
+end;
+
+architecture a of e1 is
+
+begin
+
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity e2 is
+begin
+end;
+
+architecture a of e2 is
+constant r2: integer := 10e6;
+
+signal slv2: std_logic_vector(7 downto 0);
+signal sl2: std_logic;
+begin
+tx: entity work.e1
+port map(
+r1 => real(r2_wrong),
+slv1 => slv2,
+sl1 => sl2
+);
+end;