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| author | Tristan Gingold <tgingold@free.fr> | 2015-10-23 07:54:40 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2015-10-23 07:54:40 +0200 |
| commit | ab70415983fec433dd35aea6cc8b107699a5aff0 (patch) | |
| tree | 097774b70472d912cc5ff2adb4a6314a2e31553c /testsuite/gna/ticket97/bug.vhdl | |
| parent | 978cf0e8a286d2cec52d8f33a70040dce8610bdb (diff) | |
| download | ghdl-ab70415983fec433dd35aea6cc8b107699a5aff0.tar.gz ghdl-ab70415983fec433dd35aea6cc8b107699a5aff0.tar.bz2 ghdl-ab70415983fec433dd35aea6cc8b107699a5aff0.zip | |
Add reproducer for ticket97
Diffstat (limited to 'testsuite/gna/ticket97/bug.vhdl')
| -rw-r--r-- | testsuite/gna/ticket97/bug.vhdl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/gna/ticket97/bug.vhdl b/testsuite/gna/ticket97/bug.vhdl new file mode 100644 index 000000000..6364a6643 --- /dev/null +++ b/testsuite/gna/ticket97/bug.vhdl @@ -0,0 +1,19 @@ +library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity foo is end entity;
+architecture arch of foo is
+begin
+ process is
+ procedure xyzzy( v : inout unsigned ) is
+ begin
+ v := v + 1;
+ end procedure;
+
+ variable x : std_ulogic_vector( 7 downto 0 );
+ begin
+ -- trying to do an inout conversion triggers the bug:
+ xyzzy( std_ulogic_vector( v ) => unsigned( x ) );
+ wait;
+ end process;
+end architecture;
|