testsuite/gna: add a test for #852

3 files changed, 71 insertions, 44 deletions

diff --git a/testsuite/gna/issue852/tb.vhdl b/testsuite/gna/issue852/recordofrecord_tb.vhdl
index 9fc3b07c5..f9463ebb3 100644
--- a/testsuite/gna/issue852/tb.vhdl
+++ b/testsuite/gna/issue852/recordofrecord_tb.vhdl
@@ -1,7 +1,7 @@
 library ieee;
     use ieee.std_logic_1164.all;
     use ieee.numeric_std.all;
-    
+
 entity recordOfRecord_tb is
   generic
   (       NB_CHAN_G : positive := 2
@@ -9,59 +9,59 @@ entity recordOfRecord_tb is
    ;      W_DAT_G   : positive := 16
   );
 end recordOfRecord_tb;
-architecture tb of recordOfRecord_tb  is 
-  type dmn_t is record 
+architecture tb of recordOfRecord_tb  is
+  type dmn_t is record
     clk: std_ulogic;
     rst: std_ulogic;
   end record;
 
   signal dmn_i_s : dmn_t;
   signal stop_s : std_logic := '0';
-  
+
   type fifo_i_t is record
-    rx_cyc   : std_ulogic;                     
-    rx_stb   : std_ulogic;                     
-    rx_tga   : std_ulogic_vector;              
+    rx_cyc   : std_ulogic;
+    rx_stb   : std_ulogic;
+    rx_tga   : std_ulogic_vector;
     rx_cti   : std_ulogic_vector( 1 downto 0 );
-    rx_dat   : std_ulogic_vector;              
-    tx_ack   : std_ulogic;                     
-    tx_stall : std_ulogic;   
+    rx_dat   : std_ulogic_vector;
+    tx_ack   : std_ulogic;
+    tx_stall : std_ulogic;
   end record;
-  
+
   type fifo_o_t is record
-    rx_ack   : std_ulogic;                      
-    rx_stall : std_ulogic; 
-    tx_cyc   : std_ulogic;                      
-    tx_stb   : std_ulogic;                      
-    tx_tga   : std_ulogic_vector;               
-    tx_cti   : std_ulogic_vector( 1 downto 0 ); 
-    tx_dat   : std_ulogic_vector;               
+    rx_ack   : std_ulogic;
+    rx_stall : std_ulogic;
+    tx_cyc   : std_ulogic;
+    tx_stb   : std_ulogic;
+    tx_tga   : std_ulogic_vector;
+    tx_cti   : std_ulogic_vector( 1 downto 0 );
+    tx_dat   : std_ulogic_vector;
   end record;
-  
+
   type fifo_array_i_t is array ( natural range <> ) of fifo_i_t;
-  type fifo_array_o_t is array ( natural range <> ) of fifo_o_t; 
-  
-  signal arr_fifo_o 
+  type fifo_array_o_t is array ( natural range <> ) of fifo_o_t;
+
+  signal arr_fifo_o
   : fifo_array_o_t( 0 to NB_CHAN_G - 1 )
-   (   tx_tga( W_ADR_G - 1 downto 0 ) 
+   (   tx_tga( W_ADR_G - 1 downto 0 )
    ,   tx_dat( W_DAT_G - 1 downto 0 )
   );
 
   type reg_t is record
 
-    arr_fifo_i 
+    arr_fifo_i
     : fifo_array_i_t( 0 to NB_CHAN_G - 1 )
-     (   rx_tga( W_ADR_G - 1 downto 0 ) 
+     (   rx_tga( W_ADR_G - 1 downto 0 )
      ,   rx_dat( W_DAT_G - 1 downto 0 )
-    );  
+    );
 
   end record;
-    
+
   signal a
   ,      r
   : reg_t;
-begin 
-  
+begin
+
   process
   begin
     dmn_i_s.clk <= '0';
@@ -72,7 +72,7 @@ begin
       wait;
     end if;
   end process;
-  
+
   process
   begin
     dmn_i_s.rst <= '1';
@@ -80,7 +80,7 @@ begin
     dmn_i_s.rst <= '0';
     wait;
   end process;
-  
+
   process
   begin
     arr_fifo_o( 0 ).tx_cyc <= '0';
@@ -106,23 +106,23 @@ begin
       if arr_fifo_o( 0 ).tx_cyc = '1' and r.arr_fifo_i( 0 ).tx_ack = '1' then
         a_v.arr_fifo_i( 0 ).tx_ack := '0';
       else
-        a_v.arr_fifo_i( 0 ).tx_ack := '1' and arr_fifo_o( 0 ).tx_cyc;  
+        a_v.arr_fifo_i( 0 ).tx_ack := '1' and arr_fifo_o( 0 ).tx_cyc;
       end if;
     else
       a_v.arr_fifo_i( 0 ).tx_ack := arr_fifo_o( 0 ).tx_cyc;
     end if;
 
     if dmn_i_s.rst = '1' then
-      a_v.arr_fifo_i( 0 ).tx_ack := '0'; 
+      a_v.arr_fifo_i( 0 ).tx_ack := '0';
     end if;
-    
+
     a <= a_v;
   end process;
-  
+
 
   process( dmn_i_s.clk )
-  begin 
-    if rising_edge( dmn_i_s.clk ) then 
+  begin
+    if rising_edge( dmn_i_s.clk ) then
       r <= a;
     end if;
   end process;
diff --git a/testsuite/gna/issue852/repro1.vhdl b/testsuite/gna/issue852/repro1.vhdl
new file mode 100644
index 000000000..32aacee45
--- /dev/null
+++ b/testsuite/gna/issue852/repro1.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+
+entity repro1 is
+  generic
+  (       NB_CHAN_G : positive := 2
+   ;      W_DAT_G   : positive := 16
+  );
+end;
+
+architecture tb of repro1  is
+  type fifo_o_t is record
+    rx_ack   : std_ulogic;
+    tx_cti   : std_ulogic_vector( 1 downto 0 );
+    tx_dat   : std_ulogic_vector;
+  end record;
+
+  type fifo_array_o_t is array ( natural range <> ) of fifo_o_t;
+
+  signal arr_fifo_o :
+    fifo_array_o_t(0 to NB_CHAN_G - 1) (tx_dat(W_DAT_G - 1 downto 0));
+begin
+end tb;
diff --git a/testsuite/gna/issue852/testsuite.sh b/testsuite/gna/issue852/testsuite.sh
index 1aee9143e..ac6e49750 100755
--- a/testsuite/gna/issue852/testsuite.sh
+++ b/testsuite/gna/issue852/testsuite.sh
@@ -3,13 +3,17 @@
 . ../../testenv.sh
 
 export GHDL_STD_FLAGS=--std=08
-analyze tb.vhdl
-elab recordOfRecord_tb
-if ghdl_has_feature recordofrecord_tb ghw; then
-  simulate recordOfRecord_tb --wave=recordOfRecord_tb.ghw
-else
-  simulate recordOfRecord_tb
-fi
+for f in repro1 recordofrecord_tb; do
+  analyze $f.vhdl
+  elab $f
+
+  if ghdl_has_feature $f ghw; then
+    simulate $f --dump-rti
+    simulate $f --wave=$f.ghw
+    rm -f $f.ghw
+  fi
+done
+
 clean
 
 echo "Test successful"