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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-11 04:20:25 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-11 04:20:25 +0200 |
| commit | 65258e6094ee8932412dea18c822cdcba1d0ed16 (patch) | |
| tree | 9e90c9d3d1a85dcc211214844562bf53e4334ed0 /testsuite/gna | |
| parent | 2acb520468f80a77a8ee5bd05203e297db1a894f (diff) | |
| download | ghdl-65258e6094ee8932412dea18c822cdcba1d0ed16.tar.gz ghdl-65258e6094ee8932412dea18c822cdcba1d0ed16.tar.bz2 ghdl-65258e6094ee8932412dea18c822cdcba1d0ed16.zip | |
testsuite/gna: add a test for #2112
Diffstat (limited to 'testsuite/gna')
| -rw-r--r-- | testsuite/gna/issue2112/abc.vhdl | 49 | ||||
| -rw-r--r-- | testsuite/gna/issue2112/abc_tb.vhdl | 41 | ||||
| -rw-r--r-- | testsuite/gna/issue2112/abc_tb1.vhdl | 41 | ||||
| -rw-r--r-- | testsuite/gna/issue2112/abc_tb2.vhdl | 13 | ||||
| -rw-r--r-- | testsuite/gna/issue2112/abc_tb3.vhdl | 10 | ||||
| -rwxr-xr-x | testsuite/gna/issue2112/testsuite.sh | 21 |
6 files changed, 175 insertions, 0 deletions
diff --git a/testsuite/gna/issue2112/abc.vhdl b/testsuite/gna/issue2112/abc.vhdl new file mode 100644 index 000000000..137bacf81 --- /dev/null +++ b/testsuite/gna/issue2112/abc.vhdl @@ -0,0 +1,49 @@ +library ieee;
+use ieee.std_logic_1164.all;
+
+package abc is
+ type Parameters_t is record
+ BW : natural;
+ PAIRS : natural;
+ end record;
+
+ type Indices_t is array (natural range <>) of std_logic_vector;
+
+ type Bus_t is record
+ Indices : Indices_t;
+ end record;
+
+ function Test(
+ abc_bus : Bus_t
+ ) return Bus_t;
+
+ function Test(
+ abc_bus : Bus_t;
+ indices : Indices_t
+ ) return Bus_t;
+end package;
+
+package body abc is
+ function Test(
+ abc_bus : Bus_t;
+ indices : Indices_t
+ ) return Bus_t is
+ variable result : Bus_t(
+ Indices(abc_bus.Indices'range)(abc_bus.Indices'element'range)
+ ) := Test(abc_bus);
+ begin
+ return result;
+ end function;
+
+ function Test(
+ abc_bus : Bus_t
+ ) return Bus_t is
+ variable result : Bus_t(
+ Indices(abc_bus.Indices'range)(abc_bus.Indices'element'range)
+ ) := abc_bus;
+ begin
+ return result;
+ end function;
+end package body;
+
+
diff --git a/testsuite/gna/issue2112/abc_tb.vhdl b/testsuite/gna/issue2112/abc_tb.vhdl new file mode 100644 index 000000000..23178d895 --- /dev/null +++ b/testsuite/gna/issue2112/abc_tb.vhdl @@ -0,0 +1,41 @@ +library ieee;
+use ieee.std_logic_1164.all;
+
+use work.abc;
+use work.abc.all;
+
+use std.env.finish;
+
+entity abc_tb is
+end entity abc_tb;
+
+architecture sim of abc_tb is
+ constant CLK_PERIOD : time := 10 ns;
+
+ signal clk : std_ulogic := '0';
+
+ constant abc_BUS_SETTINGS : abc.Parameters_t := (
+ BW => 8,
+ PAIRS => 2
+ );
+
+ signal abc_bus : abc.Bus_t(
+ Indices(abc_BUS_SETTINGS.PAIRS - 1 downto 0)(abc_BUS_SETTINGS.BW - 1 downto 0)
+ );
+
+begin
+ clk <= not clk after CLK_PERIOD / 2;
+ test_runner : process
+ begin
+ abc_bus <= abc.Test(
+ abc_bus,
+ (
+ 0 => std_logic_vector'(x"00"),
+ 1 => std_logic_vector'(x"01")
+ )
+ );
+ wait for CLK_PERIOD;
+ finish;
+ end process test_runner;
+
+end architecture sim;
diff --git a/testsuite/gna/issue2112/abc_tb1.vhdl b/testsuite/gna/issue2112/abc_tb1.vhdl new file mode 100644 index 000000000..46754b832 --- /dev/null +++ b/testsuite/gna/issue2112/abc_tb1.vhdl @@ -0,0 +1,41 @@ +library ieee;
+use ieee.std_logic_1164.all;
+
+use work.abc;
+use work.abc.all;
+
+use std.env.finish;
+
+entity abc_tb1 is
+end entity abc_tb1;
+
+architecture sim of abc_tb1 is
+ constant CLK_PERIOD : time := 10 ns;
+
+ signal clk : std_ulogic := '0';
+
+ constant abc_BUS_SETTINGS : abc.Parameters_t := (
+ BW => 8,
+ PAIRS => 2
+ );
+
+ signal abc_bus : abc.Bus_t(
+ Indices(abc_BUS_SETTINGS.PAIRS - 1 downto 0)(abc_BUS_SETTINGS.BW - 1 downto 0)
+ );
+
+begin
+ clk <= not clk after CLK_PERIOD / 2;
+ test_runner : process
+ begin
+ abc_bus <= abc.Test(
+ abc_bus,
+ (
+ 0 => x"00",
+ 1 => x"01"
+ )
+ );
+ wait for CLK_PERIOD;
+ finish;
+ end process test_runner;
+
+end architecture sim;
diff --git a/testsuite/gna/issue2112/abc_tb2.vhdl b/testsuite/gna/issue2112/abc_tb2.vhdl new file mode 100644 index 000000000..ea27127db --- /dev/null +++ b/testsuite/gna/issue2112/abc_tb2.vhdl @@ -0,0 +1,13 @@ +library ieee;
+use ieee.std_logic_1164.all;
+
+entity abc_tb2 is
+end;
+
+architecture sim of abc_tb2 is
+ type Indices_t is array (natural range <>) of std_logic_vector;
+
+ constant c : Indices_t := (0 => std_logic_vector'(x"00"),
+ 1 => std_logic_vector'(x"01"));
+begin
+end architecture sim;
diff --git a/testsuite/gna/issue2112/abc_tb3.vhdl b/testsuite/gna/issue2112/abc_tb3.vhdl new file mode 100644 index 000000000..17526c5d5 --- /dev/null +++ b/testsuite/gna/issue2112/abc_tb3.vhdl @@ -0,0 +1,10 @@ +entity abc_tb3 is
+end;
+
+architecture sim of abc_tb3 is
+ type Indices_t is array (natural range <>) of bit_vector;
+
+ constant c : Indices_t := (0 => bit_vector'(x"00"),
+ 1 => bit_vector'(x"01"));
+begin
+end architecture sim;
diff --git a/testsuite/gna/issue2112/testsuite.sh b/testsuite/gna/issue2112/testsuite.sh new file mode 100755 index 000000000..2f9720f3c --- /dev/null +++ b/testsuite/gna/issue2112/testsuite.sh @@ -0,0 +1,21 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze abc.vhdl +analyze abc_tb.vhdl +elab_simulate abc_tb + +analyze abc_tb1.vhdl +elab_simulate abc_tb1 + +analyze abc_tb2.vhdl +elab_simulate abc_tb2 + +analyze abc_tb3.vhdl +elab_simulate abc_tb3 + +clean + +echo "Test successful" |