Add testcase for issue #144

2 files changed, 19 insertions, 0 deletions

diff --git a/testsuite/gna/issue144/tb.vhdl b/testsuite/gna/issue144/tb.vhdl
new file mode 100644
index 000000000..1a89c3123
--- /dev/null
+++ b/testsuite/gna/issue144/tb.vhdl
@@ -0,0 +1,10 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity A_tb is
+end entity;
+
+architecture A_tb_impl of A_tb is
+begin
+  a : work.a(a) port map(a => a);  -- syntax error here, missing 'entity'
+end architecture;
diff --git a/testsuite/gna/issue144/testsuite.sh b/testsuite/gna/issue144/testsuite.sh
new file mode 100755
index 000000000..8a9a6eed3
--- /dev/null
+++ b/testsuite/gna/issue144/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure tb.vhdl
+
+clean
+
+echo "Test successful"