Add a test for vcd and fst dumps.

2 files changed, 58 insertions, 0 deletions

diff --git a/testsuite/gna/bug045/repro.vhdl b/testsuite/gna/bug045/repro.vhdl
new file mode 100644
index 000000000..9f53c3f2e
--- /dev/null
+++ b/testsuite/gna/bug045/repro.vhdl
@@ -0,0 +1,41 @@
+entity sub is
+  generic (l : natural);
+  port (a : out bit;
+        b : bit_vector (0 to 3);
+        c : bit_vector (0 to l - 1));
+end sub;
+
+architecture behav of sub is
+begin
+  a <= b (0) xor c (0);
+end behav;
+
+entity tb is
+end tb;
+
+architecture behav of tb is
+  signal a : bit;
+  signal b: bit_vector (0 to 3);
+  signal c: bit_vector (0 to 7);
+
+  type state is (S0, S1, S_done);
+  signal s : state := S0;
+begin
+  my_sub: entity work.sub
+    generic map (l => c'length)
+    port map (a => a, b => b, c => c);
+
+  process
+  begin
+    wait for 1 ns;
+    assert a = '0';
+    b <= x"0";
+    c <= x"80";
+    s <= s1;
+    wait for 1 ns;
+    assert a = '1';
+    s <= S_done;
+    wait for 1 ns;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/bug045/testsuite.sh b/testsuite/gna/bug045/testsuite.sh
new file mode 100755
index 000000000..7f3c77360
--- /dev/null
+++ b/testsuite/gna/bug045/testsuite.sh
@@ -0,0 +1,17 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze repro.vhdl
+elab tb
+if ghdl_has_feature tb fst; then
+  simulate tb --fst=tb.fst
+fi
+if ghdl_has_feature tb vcd; then
+  simulate tb --vcd=tb.vcd
+fi
+
+clean
+rm -f tb.fst tb.vcd
+
+echo "Test successful"