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author | Tristan Gingold <tgingold@free.fr> | 2017-06-27 20:02:10 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-06-27 20:02:10 +0200 |
commit | f53677c01460f1d707ddc10d2bac9872b520460e (patch) | |
tree | e9e07243828ad74631616b2df8e62800369d9695 /testsuite/gna | |
parent | f0d19c32c5f4b0ae7ac47599ef917cf717cdd5f3 (diff) | |
download | ghdl-f53677c01460f1d707ddc10d2bac9872b520460e.tar.gz ghdl-f53677c01460f1d707ddc10d2bac9872b520460e.tar.bz2 ghdl-f53677c01460f1d707ddc10d2bac9872b520460e.zip |
Add testcase for #373
Diffstat (limited to 'testsuite/gna')
-rw-r--r-- | testsuite/gna/issue373/e.vhdl | 20 | ||||
-rwxr-xr-x | testsuite/gna/issue373/testsuite.sh | 10 |
2 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/gna/issue373/e.vhdl b/testsuite/gna/issue373/e.vhdl new file mode 100644 index 000000000..395e8c6e9 --- /dev/null +++ b/testsuite/gna/issue373/e.vhdl @@ -0,0 +1,20 @@ +entity x is + port( + t :out bit_vector(0 to 0); + z :out bit_vector(0 to 0) + ); +end entity; +architecture a of x is begin end architecture; + +entity e is end entity; +architecture a of e is + constant z :integer := 0; + subtype t is bit_vector(0 to 0); + signal actual_for_t :bit; + signal actual_for_z :t; +begin + inst: entity work.x port map( + t(z) => actual_for_t, + t(z) => actual_for_z + ); +end architecture; diff --git a/testsuite/gna/issue373/testsuite.sh b/testsuite/gna/issue373/testsuite.sh new file mode 100755 index 000000000..57536e34f --- /dev/null +++ b/testsuite/gna/issue373/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze e.vhdl +elab_simulate e + +clean + +echo "Test successful" |