Add bug16695

3 files changed, 163 insertions, 0 deletions

diff --git a/testsuite/gna/bug16695/lfsr_updown.vhd b/testsuite/gna/bug16695/lfsr_updown.vhd
new file mode 100644
index 000000000..ace8956d3
--- /dev/null
+++ b/testsuite/gna/bug16695/lfsr_updown.vhd
@@ -0,0 +1,65 @@
+-------------------------------------------------------
+-- Design Name : lfsr
+-- File Name   : lfsr_updown.vhd
+-- Function    : Linear feedback shift register
+-- Coder       : Deepak Kumar Tala (Verilog)
+-- Translator  : Alexander H Pham (VHDL)
+-------------------------------------------------------
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+entity lfsr_updown is
+    generic (
+        WIDTH :integer := 8
+    );
+    port (
+        clk       :in  std_logic;                       -- Clock input
+        reset     :in  std_logic;                       -- Reset input
+        enable    :in  std_logic;                       -- Enable input
+        up_down   :in  std_logic;                       -- Up Down input
+        count     :out std_logic_vector (WIDTH-1 downto 0);   -- Count output
+        overflow  :out std_logic                        -- Overflow output
+    );
+end entity;
+
+architecture rtl of lfsr_updown is
+    signal cnt :std_logic_vector (WIDTH-1 downto 0);
+begin
+
+    process (up_down, cnt) begin
+        if (((up_down = '1') and (cnt(WIDTH-1) = '1')) or
+            ((up_down = '0') and ((cnt(WIDTH-1) = '1') and 
+	    (cnt(WIDTH-2 downto 0) = "0")))) then
+            overflow <= '1';
+        else
+            overflow <= '0';
+        end if;
+    end process;
+    
+    process (clk, reset, cnt, enable, up_down)
+        variable temp_a :std_logic_vector (WIDTH-1 downto 0);
+        variable temp_b :std_logic :='1';
+    begin
+    
+        temp_a := cnt and "01100011";
+        temp_b :='1';
+        for i in 0 to WIDTH-1 loop
+            temp_b := temp_a(i) xnor temp_b;
+        end loop;
+
+        if (rising_edge(clk)) then
+            if (reset = '1') then
+                cnt <= (others=>'0');
+            elsif (enable = '1') then
+                if (up_down = '1') then
+                    cnt <= (temp_b & cnt(WIDTH-1 downto 1));
+                else
+                    cnt <= (cnt(WIDTH-2 downto 0) & temp_b);
+                end if;
+            end if;
+        end if;
+    end process;
+    count <= cnt;
+    
+end architecture;
diff --git a/testsuite/gna/bug16695/lfsr_updown_tb.vhd b/testsuite/gna/bug16695/lfsr_updown_tb.vhd
new file mode 100644
index 000000000..30bf759b3
--- /dev/null
+++ b/testsuite/gna/bug16695/lfsr_updown_tb.vhd
@@ -0,0 +1,88 @@
+-------------------------------------------------------
+-- Design Name : lfsr
+-- File Name   : lfsr_updown_tb.vhd
+-- Function    : Linear feedback shift register
+-- Coder       : Deepak Kumar Tala (Verilog)
+-- Translator  : Alexander H Pham (VHDL)
+-------------------------------------------------------
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.std_logic_textio.all;
+    use std.textio.all;
+    
+entity lfsr_updown_tb is
+end entity;
+architecture test of lfsr_updown_tb is
+
+    constant WIDTH :integer := 8;
+
+    signal clk       :std_logic := '0';
+    signal reset     :std_logic := '1';
+    signal enable    :std_logic := '0';
+    signal up_down   :std_logic := '0';
+    signal count     :std_logic_vector (WIDTH-1 downto 0);
+    signal overflow  :std_logic;
+    
+    component lfsr_updown is
+    generic (
+        WIDTH :integer := 8
+    );
+    port (
+        clk       :in  std_logic;                       -- Clock input
+        reset     :in  std_logic;                       -- Reset input
+        enable    :in  std_logic;                       -- Enable input
+        up_down   :in  std_logic;                       -- Up Down input
+        count     :out std_logic_vector (WIDTH-1 downto 0);   -- Count output
+        overflow  :out std_logic                        -- Overflow output
+    );
+    end component;
+    
+    constant PERIOD :time := 20 ns;
+    
+begin
+    clk     <= not clk after PERIOD/2;
+    reset   <= '0' after PERIOD*10;
+    enable  <= '1' after PERIOD*11;
+    up_down <= '1' after PERIOD*22;
+    
+    -- Display the time and result
+    process (reset, enable, up_down, count, overflow)
+        variable wrbuf :line;
+    begin
+        write(wrbuf, string'("Time: "     )); 
+        writeline(output, wrbuf);
+	write(wrbuf, now);
+        writeline(output, wrbuf);
+        write(wrbuf, string'(" rst: "     )); 
+        writeline(output, wrbuf);
+	write(wrbuf, reset);
+        writeline(output, wrbuf);
+        write(wrbuf, string'(" enable: "  )); 
+        writeline(output, wrbuf);
+	write(wrbuf, enable);
+        writeline(output, wrbuf);
+        write(wrbuf, string'(" up_down: " )); 
+        writeline(output, wrbuf);
+	write(wrbuf, up_down);
+        writeline(output, wrbuf);
+        write(wrbuf, string'(" count: "   )); 
+        writeline(output, wrbuf);
+	write(wrbuf, count);
+        writeline(output, wrbuf);
+        write(wrbuf, string'(" overflow: ")); 
+        writeline(output, wrbuf);
+	write(wrbuf, overflow);
+        writeline(output, wrbuf);
+    end process;
+
+    Inst_lfsr_updown : lfsr_updown
+    port map (
+        clk      => clk,
+        reset    => reset,
+        enable   => enable,
+        up_down  => up_down,
+        count    => count,
+        overflow => overflow
+    );
+
+end architecture;
diff --git a/testsuite/gna/bug16695/testsuite.sh b/testsuite/gna/bug16695/testsuite.sh
new file mode 100755
index 000000000..4caea3335
--- /dev/null
+++ b/testsuite/gna/bug16695/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze --ieee=synopsys lfsr_updown.vhd lfsr_updown_tb.vhd
+elab_simulate --ieee=synopsys lfsr_updown_tb --stop-time=200ns
+
+clean
+
+echo "Test successful"