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author | Unai Martinez-Corral <38422348+umarcor@users.noreply.github.com> | 2021-06-23 16:07:10 +0100 |
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committer | GitHub <noreply@github.com> | 2021-06-23 16:07:10 +0100 |
commit | c6283d9a9b40c3e9afeba912fcb13aa9d56b9c52 (patch) | |
tree | e1706cb19a2439e3d94657e54c688a36c703f048 /testsuite/pyunit/Current.vhdl | |
parent | 983236ac3dfd0c455a0ac910a9a468ea2c81e5d9 (diff) | |
parent | 240b4fdd90a9f3ca04e8e168bffdc92bea2ca3f3 (diff) | |
download | ghdl-c6283d9a9b40c3e9afeba912fcb13aa9d56b9c52.tar.gz ghdl-c6283d9a9b40c3e9afeba912fcb13aa9d56b9c52.tar.bz2 ghdl-c6283d9a9b40c3e9afeba912fcb13aa9d56b9c52.zip |
DOM: Functions and types (#1804)
Diffstat (limited to 'testsuite/pyunit/Current.vhdl')
-rw-r--r-- | testsuite/pyunit/Current.vhdl | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 8653cb088..ff03e1d04 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -20,16 +20,36 @@ end entity entity_1; architecture behav of entity_1 is constant MAX : positive := -25; - signal rst : std_logic := foo'('U'); + signal rst : std_logic := foo('U'); +-- signal vec : bit_vector(pack.input'bar'range); type newInt is range -4 to 3; + type newFp is range 4.3 downto -3.9; + type arr is array(natural range <>, enum range <>) of integer(3 downto 0); + type rec is record + elem1 : bit; + elem2 : boolean; + elem3 : integer_vector(3 downto 0); + elem4 : natural range 7 to 8; + end record; + type enum is (e1, e2, e3); + type acc is access bar; subtype uint8 is integer range 0 to 255; - function foo(a : integer; b : boolean) return bit is +-- file f : text; + + function func (a : integer; b : boolean) return bit is begin end function; + shared variable pt_var : lib.pack.prot; + + procedure proc(spam : egg) is + begin + + end procedure; + alias bar is boolean; begin process(Clock) @@ -46,6 +66,12 @@ end architecture behav; package package_1 is constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10); -- 2.3; + + component comp is + port ( + clk : std + ); + end component; end package; package body package_1 is |