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author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-19 12:14:18 +0200 |
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committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-06-19 15:25:07 +0200 |
commit | f683303868a941b02535aab4a989b2f916624a26 (patch) | |
tree | 4f866bc56d7aed027eba00cca6670d7c931604ee /testsuite/pyunit/dom/Expressions.py | |
parent | ef0dbc726749df434036b23480b89f01cbe67d44 (diff) | |
download | ghdl-f683303868a941b02535aab4a989b2f916624a26.tar.gz ghdl-f683303868a941b02535aab4a989b2f916624a26.tar.bz2 ghdl-f683303868a941b02535aab4a989b2f916624a26.zip |
Simplified prettyprint, as pyVHDLModel has now builtin __str__ methods for expressions, aggregates and literals.
Diffstat (limited to 'testsuite/pyunit/dom/Expressions.py')
-rw-r--r-- | testsuite/pyunit/dom/Expressions.py | 39 |
1 files changed, 30 insertions, 9 deletions
diff --git a/testsuite/pyunit/dom/Expressions.py b/testsuite/pyunit/dom/Expressions.py index 8ef013ef7..3a4f658af 100644 --- a/testsuite/pyunit/dom/Expressions.py +++ b/testsuite/pyunit/dom/Expressions.py @@ -2,6 +2,8 @@ from pathlib import Path from textwrap import dedent from unittest import TestCase +from pyGHDL.dom.DesignUnit import Package + from pyGHDL.dom import Expression from pyGHDL.dom.Misc import Design, Document from pyGHDL.dom.Symbol import SimpleObjectSymbol @@ -33,17 +35,36 @@ class Expressions(TestCase): document = Document(self._filename) design.Documents.append(document) - self.assertEqual(len(design.Documents[0].Packages), 1) - package = design.Documents[0].Packages[0] - self.assertTrue(package.Name == "package_1") - self.assertEqual(len(package.DeclaredItems), 1) - + package: Package = design.Documents[0].Packages[0] item: Constant = package.DeclaredItems[0] - self.assertTrue(isinstance(item, Constant)) - self.assertTrue(item.Name == "c0") - self.assertTrue(item.SubType.SymbolName == "boolean") - default: Expression = item.DefaultExpression self.assertTrue(isinstance(default, InverseExpression)) self.assertTrue(isinstance(default.Operand, SimpleObjectSymbol)) self.assertTrue(default.Operand.SymbolName == "true") + + # def test_Aggregare(self): + # self._filename: Path = self._root / "{className}.vhdl".format(className=self.__class__.__name__) + # + # sourceCode = dedent("""\ + # package package_1 is + # constant c0 : integer_vector := (0, 1, 2); 0 =>); + # constant c1 : integer_vector := (0 => 0, 1 => 1, 2 => 2); + # constant c3 : integer_vector := (a => 0, b => 1, c => 2); + # constant c3 : integer_vector := (0 to 2 => 3, 3 to 4 => 2); + # constant c2 : integer_vector := (others => 0); + # end package; + # """) + # + # with self._filename.open(mode="w", encoding="utf-8") as file: + # file.write(sourceCode) + # + # design = Design() + # document = Document(self._filename) + # design.Documents.append(document) + # + # package: Package = design.Documents[0].Packages[0] + # item: Constant = package.DeclaredItems[0] + # default: Expression = item.DefaultExpression + # self.assertTrue(isinstance(default, InverseExpression)) + # self.assertTrue(isinstance(default.Operand, SimpleObjectSymbol)) + # self.assertTrue(default.Operand.SymbolName == "true") |