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authorUnai Martinez-Corral <38422348+umarcor@users.noreply.github.com>2021-08-23 17:04:46 +0100
committerGitHub <noreply@github.com>2021-08-23 17:04:46 +0100
commitdac2e4dca824f413821962eeac314ceaf56925a7 (patch)
tree69575b8939b2d550b7f92f0d23e4a0b854dff283 /testsuite/pyunit/dom/Literals.py
parent9df82e519d7e93168d43fb414c48c9e547b0c306 (diff)
parentb229fa55b6485350ced8e31d6a803d08544b6d22 (diff)
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pyGHDL: update to pyVHDLModel v0.11.5 (#1822)
New Features: * Handle multiple identifiers in generics, ports, parameters and objects. * `ghdl-dom` now also accepts `-D` for directories to scan. * Resolve architectures to entities. * Context reference * Library clause * Use clause * Handle contexts of design units * New `OpenName` * Translate concurrent statements: * Component instantiation * Entity instantiation * Configuration instantiation * If..generate statement * Case..generate statement * For..generate statement * Block statement * Process statement * Concurrent simple signal assignment * Concurrent procedure call * Translate sequential statements: * If statement * Case statement * For loop * Sequential simple signal assignment * Sequential procedure call * Sequential assert statement * Sequential report statement * Wait statement * Print hierarchy in pretty-print * New binding to `str_table` `string8_address` Changes: * Adjusted to renaming of `pyVHDLModel.VHDLModel` to `pyVHDLModel.SyntaxModel`. * Adjust DOM to a change in pyVHDLModel: some Identifiers being now a list of identifiers. * Reordered items in GHA workflow `Test.yml`. * Improved ranges Bug fixes: * Fixed typo in IIR translation of `Greater_Than_Or_Equal_Operator`: should be `GreaterEqualExpression`. * Wrap type marks in a `SimpleName`. * Fixed syntax of lists in GHA workflow `Test.yml`. * Fixed handling of bit-string literals.
Diffstat (limited to 'testsuite/pyunit/dom/Literals.py')
-rw-r--r--testsuite/pyunit/dom/Literals.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/testsuite/pyunit/dom/Literals.py b/testsuite/pyunit/dom/Literals.py
index 418a1b76d..debd401e3 100644
--- a/testsuite/pyunit/dom/Literals.py
+++ b/testsuite/pyunit/dom/Literals.py
@@ -34,7 +34,7 @@ from pathlib import Path
from textwrap import dedent
from unittest import TestCase
-from pyVHDLModel.VHDLModel import Expression
+from pyVHDLModel.SyntaxModel import ExpressionUnion
from pyGHDL.dom.DesignUnit import Package
@@ -60,7 +60,7 @@ class Literals(TestCase):
"""
)
- def parse(self, filename: Path, code: str) -> Expression:
+ def parse(self, filename: Path, code: str) -> ExpressionUnion:
sourceCode = self._packageTemplate.format(code=code)
document = Document(filename, sourceCode)
@@ -69,7 +69,7 @@ class Literals(TestCase):
# Traverse already to default value expression
package: Package = document.Packages[0]
item: Constant = package.DeclaredItems[0]
- default: Expression = item.DefaultExpression
+ default: ExpressionUnion = item.DefaultExpression
return default
@@ -82,7 +82,7 @@ class Literals(TestCase):
expected = (0, 1, 1024, 1048576)
# Parse in-memory
- default: Expression = self.parse(_filename, constantDeclartion)
+ default: ExpressionUnion = self.parse(_filename, constantDeclartion)
self.assertIsInstance(default, IntegerLiteral)
self.assertEqual(expected[0], default.Value)