Updated to pyVHDLModel v0.18.0.

1 files changed, 9 insertions, 1 deletions

diff --git a/testsuite/pyunit/dom/Literals.py b/testsuite/pyunit/dom/Literals.py
index debd401e3..9f53a6cc6 100644
--- a/testsuite/pyunit/dom/Literals.py
+++ b/testsuite/pyunit/dom/Literals.py
@@ -32,6 +32,7 @@
 # ============================================================================
 from pathlib import Path
 from textwrap import dedent
+from typing import TypeVar, Dict
 from unittest import TestCase
 
 from pyVHDLModel.SyntaxModel import ExpressionUnion
@@ -49,6 +50,13 @@ if __name__ == "__main__":
     exit(1)
 
 
+_DictKey = TypeVar("_DictKey")
+_DictValue = TypeVar("_DictValue")
+
+def firstValue(d: Dict[_DictKey, _DictValue]) -> _DictValue:
+    return next(iter(d.values()))
+
+
 class Literals(TestCase):
     _root = Path(__file__).resolve().parent.parent
     _design = Design()
@@ -67,7 +75,7 @@ class Literals(TestCase):
         self._design.Documents.append(document)
 
         # Traverse already to default value expression
-        package: Package = document.Packages[0]
+        package: Package = firstValue(document.Packages)
         item: Constant = package.DeclaredItems[0]
         default: ExpressionUnion = item.DefaultExpression