Reorganized testcases.

49 files changed, 450 insertions, 0 deletions

diff --git a/testsuite/pyunit/libghdl/examples/Complex.vhdl b/testsuite/pyunit/libghdl/examples/Complex.vhdl
new file mode 100644
index 000000000..87276a2d5
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/Complex.vhdl
@@ -0,0 +1,132 @@
+-- :e1: comments before desIgn units (javadoc / .net documentation style)
+-- :e1: mIGht be multiline
+entity e1 is
+end entitY;
+
+-- :a1: comments before design units
+-- :a1: might be multiline
+architecture a1 of e1 is
+begin
+end architecture;
+
+-- :p1: comments before design units
+-- :p1: might be multiline
+package p1 is
+end package;
+
+-- package body should be supported too to keep parity, but I have currently no usecase for it.
+
+-- :ctx1: comments before design units
+-- :ctx1: might be multiline
+context ctx1 is
+end context;
+
+-- :cfg1: comments before design units
+-- :cfg1: might be multiline
+configuration cfg1 of e1 is
+  for a1
+  end for;
+end configuration;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity e2 is
+  -- :e2: comments in design units (python doc-string style)
+    -- :e2: might be multi line
+    generic (
+      -- :FREQUENCY: comment before a generic
+        -- :FREQUENCY: might be multiline
+        constant FREQUENCY : positive;
+      constant BITS      : positive; -- :BITS: comment after a generic are mostly single line,
+                                       -- :BITS: but could be multi line too
+        -- in case comment is before and after
+        constant DEBUG     : boolean   -- :DEBUG: the after has presidency
+    );
+    port (
+      signal Clock : in std_logic    -- :Clock: same as for generics
+    );
+end entity;
+
+architecture a2 of e2 is
+  -- :a2: comments in design units (python doc-string style)
+    -- :a2: might be multi line
+begin
+
+end architecture;
+
+-- As packages define public elements like constants, types and sub-programs, we are interested in such documentation too.
+package p2 is
+  -- :p2: comments in design units (python doc-string style)
+    -- :p2: might be multi line
+
+    -- :DEBUG: comment before
+    constant DEBUG : boolean := TRUE;
+    constant SYNC_STAGES : positive := 3; -- :SYNC_STAGES: comment after
+
+    -- :AType1: comment before
+    type AType1 is array(natural range <>) of bit;
+    type AType2 is array(natural range <>) of bit; -- :AType2: comment after
+
+    -- same applies to subtype, alias, attributes, ...
+
+    -- :RType: comment before
+    type RType is record
+        -- :RType: xor comment inside
+
+        -- :elem1: per element comment before (note the comment "block" is separated by newlines)
+        elem1 : integer;
+        elem2 : integer; -- :elem2: per element comment behind
+    end record;
+
+    -- :log2: as functions are longer in definitions, it might be written before
+    function log2(param : positive) return natural;
+
+    function log2(
+        -- :log2: otoh, we also want to document parameters too (similar to a record with comments)
+
+      -- :param1: comment before
+      param1 : integer;
+        param2 : boolean  -- :param2: comment after
+    ) return natural;
+
+    -- this applies to procedures as well.
+
+
+
+end package;
+
+context ctx2 is
+  -- :ctx2: comments in design units (python doc-string style)
+    -- :ctx2: might be multi line
+end context;
+
+configuration cfg2 of e2 is
+  -- :cfg2: comments in design units (python doc-string style)
+  -- :cfg2: might be multi line
+  for a2
+  end for;
+end configuration;
+
+
+
+
+
+
+
+-- This should allow for any kind of documentation style and embedded documentation language.
+-- A real implementation might use similar rules are Python+docutils+Sphinx. Here we would e.g.
+-- document a function either before (or inside) a function declaration and use the
+--   :arg name: description
+-- syntax.
+
+
+-- :math: Package `math` provides math extensions not provided by the IEEE packages.
+package math is
+    -- :log2: Computes the logarithm to base 2.
+    -- :log2:
+    -- :log2: :arg param: Input value
+    -- :log2: :returns:   Logarithm
+    function log2(param : positive) return natural;
+end package;
diff --git a/testsuite/pyunit/libghdl/examples/comments/DesignComment.vhdl b/testsuite/pyunit/libghdl/examples/comments/DesignComment.vhdl
new file mode 100644
index 000000000..5cd555d33
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/DesignComment.vhdl
@@ -0,0 +1,14 @@
+--  No copyright for :accum: design.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity accum is
+  port (
+    --  :a: and :b: are the inputs of the adder.
+    a, b : in std_logic_vector (31 downto 0);
+    --  :res: is the result of the adder.
+    res : out std_logic_vector (31 downto 0)
+    );
+end accum;
+
diff --git a/testsuite/pyunit/libghdl/examples/comments/arch_bef.vhdl b/testsuite/pyunit/libghdl/examples/comments/arch_bef.vhdl
new file mode 100644
index 000000000..c089b1429
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/arch_bef.vhdl
@@ -0,0 +1,5 @@
+-- comments before design units :a1:
+-- might be multiline :a1:
+architecture a1 of e1 is
+begin
+end architecture;
diff --git a/testsuite/pyunit/libghdl/examples/comments/arch_inside.vhdl b/testsuite/pyunit/libghdl/examples/comments/arch_inside.vhdl
new file mode 100644
index 000000000..9e2184df3
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/arch_inside.vhdl
@@ -0,0 +1,6 @@
+architecture a2 of e2 is
+  -- comments in design units (python doc-string style) :a2:
+    --:a2: might be multi line
+begin
+
+end architecture;
diff --git a/testsuite/pyunit/libghdl/examples/comments/arch_inside_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/arch_inside_fail.vhdl
new file mode 100644
index 000000000..96002d336
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/arch_inside_fail.vhdl
@@ -0,0 +1,5 @@
+architecture a2 of e2 is
+  -- comments in design units (python doc-string style) :fail:
+begin
+
+end architecture;
diff --git a/testsuite/pyunit/libghdl/examples/comments/array.vhdl b/testsuite/pyunit/libghdl/examples/comments/array.vhdl
new file mode 100644
index 000000000..69db03d15
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/array.vhdl
@@ -0,0 +1,4 @@
+package p is
+  --  Comment for :vec:
+  type vec is array(natural) of bit_vector(0 to 1);
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/conf_bef.vhdl b/testsuite/pyunit/libghdl/examples/comments/conf_bef.vhdl
new file mode 100644
index 000000000..0dc3af77e
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/conf_bef.vhdl
@@ -0,0 +1,6 @@
+-- comments before design units :cfg1:
+-- might be multiline :cfg1:
+configuration cfg1 of e1 is
+  for a1
+  end for;
+end configuration;
diff --git a/testsuite/pyunit/libghdl/examples/comments/conf_inside.vhdl b/testsuite/pyunit/libghdl/examples/comments/conf_inside.vhdl
new file mode 100644
index 000000000..6181d572a
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/conf_inside.vhdl
@@ -0,0 +1,6 @@
+configuration cfg2 of e2 is
+  -- comments in design units (python doc-string style) :cfg2:
+  -- might be multi line :cfg2:
+  for a2
+  end for;
+end configuration;
diff --git a/testsuite/pyunit/libghdl/examples/comments/conf_inside_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/conf_inside_fail.vhdl
new file mode 100644
index 000000000..6b9b4dce3
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/conf_inside_fail.vhdl
@@ -0,0 +1,6 @@
+configuration cfg2 of e2 is
+  -- comments in design units (python doc-string style)
+  -- might be multi line
+  for a2
+  end for;
+end configuration;
diff --git a/testsuite/pyunit/libghdl/examples/comments/const.vhdl b/testsuite/pyunit/libghdl/examples/comments/const.vhdl
new file mode 100644
index 000000000..75e22ab51
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/const.vhdl
@@ -0,0 +1,4 @@
+package p is
+  --  Comment for the decl :c1:
+  constant c1 : natural := 3;
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/const_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/const_fail.vhdl
new file mode 100644
index 000000000..79b37fec5
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/const_fail.vhdl
@@ -0,0 +1,4 @@
+package p is
+  --  Comment for the decl.
+  constant c1 : natural := 3;
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/ctxt_bef.vhdl b/testsuite/pyunit/libghdl/examples/comments/ctxt_bef.vhdl
new file mode 100644
index 000000000..f7a8fd31c
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/ctxt_bef.vhdl
@@ -0,0 +1,4 @@
+-- comments before design units :ctx1:
+--:ctx1: might be multiline
+context ctx1 is
+end context;
diff --git a/testsuite/pyunit/libghdl/examples/comments/ctxt_inside.vhdl b/testsuite/pyunit/libghdl/examples/comments/ctxt_inside.vhdl
new file mode 100644
index 000000000..af7fdc37b
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/ctxt_inside.vhdl
@@ -0,0 +1,5 @@
+context ctx2 is
+  -- comments in design units (python doc-string style) :ctx2:
+    -- might be multi line :ctx2:
+end context;
+
diff --git a/testsuite/pyunit/libghdl/examples/comments/ctxt_inside_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/ctxt_inside_fail.vhdl
new file mode 100644
index 000000000..71dce9e40
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/ctxt_inside_fail.vhdl
@@ -0,0 +1,5 @@
+context ctx2 is
+  -- comments in design units (python doc-string style)
+    -- might be multi line
+end context;
+
diff --git a/testsuite/pyunit/libghdl/examples/comments/element_1.vhdl b/testsuite/pyunit/libghdl/examples/comments/element_1.vhdl
new file mode 100644
index 000000000..f88219bec
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/element_1.vhdl
@@ -0,0 +1,7 @@
+package p is
+  type rec is record
+    --  Comment for the first element :a:
+    a : bit;
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/element_2.vhdl b/testsuite/pyunit/libghdl/examples/comments/element_2.vhdl
new file mode 100644
index 000000000..324dac9db
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/element_2.vhdl
@@ -0,0 +1,7 @@
+package p is
+  type rec is record
+    a : bit;
+    --  Comment for the first element :b:
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/element_3.vhdl b/testsuite/pyunit/libghdl/examples/comments/element_3.vhdl
new file mode 100644
index 000000000..22f20349e
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/element_3.vhdl
@@ -0,0 +1,6 @@
+package p is
+  type rec is record
+    a : bit; --  Comment for :a:
+    b : bit; --  For :b:
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/element_4.vhdl b/testsuite/pyunit/libghdl/examples/comments/element_4.vhdl
new file mode 100644
index 000000000..57f5ea16b
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/element_4.vhdl
@@ -0,0 +1,7 @@
+package p is
+  type rec is record
+    a : bit; --  Comment for :a:
+    --  Also for :a:
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/elements_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/elements_fail.vhdl
new file mode 100644
index 000000000..9173524f2
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/elements_fail.vhdl
@@ -0,0 +1,7 @@
+package p is
+  type rec is record
+    --  Comment for the first element.
+    a : bit;
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/ent_arch.vhdl b/testsuite/pyunit/libghdl/examples/comments/ent_arch.vhdl
new file mode 100644
index 000000000..2283de701
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/ent_arch.vhdl
@@ -0,0 +1,10 @@
+-- :e1: comments before design units (javadoc / .net documentation style)
+-- :e1: might be multiline
+entity e1 is
+end entity;
+
+-- :a1: comments before design units
+-- :a1: might be multiline
+architecture a1 of e1 is
+begin
+end architecture;
diff --git a/testsuite/pyunit/libghdl/examples/comments/ent_bef.vhdl b/testsuite/pyunit/libghdl/examples/comments/ent_bef.vhdl
new file mode 100644
index 000000000..0fbf61d22
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/ent_bef.vhdl
@@ -0,0 +1,4 @@
+-- comments before design units (javadoc / .net documentation style) :e1:
+-- might be multiline :e1:
+entity e1 is
+end entity;
diff --git a/testsuite/pyunit/libghdl/examples/comments/ent_inside.vhdl b/testsuite/pyunit/libghdl/examples/comments/ent_inside.vhdl
new file mode 100644
index 000000000..834eaa999
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/ent_inside.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity e2 is
+  -- comments in design units (python doc-string style) :e2:
+    -- might be multi line :e2:
+    generic (
+      -- comment before a generic :frequency:
+        -- might be multiline :frequency:
+        constant FREQUENCY : positive
+    );
+    port (
+      signal Clock : in std_logic
+    );
+end entity;
diff --git a/testsuite/pyunit/libghdl/examples/comments/enum.vhdl b/testsuite/pyunit/libghdl/examples/comments/enum.vhdl
new file mode 100644
index 000000000..320f0a7dc
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/enum.vhdl
@@ -0,0 +1,4 @@
+package p is
+  --  Comment for :state_t:
+  type state_t is (s1, s2, s3);
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/enum_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/enum_fail.vhdl
new file mode 100644
index 000000000..51ebfac86
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/enum_fail.vhdl
@@ -0,0 +1,4 @@
+package p is
+  --  Comment
+  type state_t is (s1, s2, s3);
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/enumlit_1.vhdl b/testsuite/pyunit/libghdl/examples/comments/enumlit_1.vhdl
new file mode 100644
index 000000000..c9b923051
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/enumlit_1.vhdl
@@ -0,0 +1,8 @@
+package p is
+  type state_t is
+    (
+      --  Comment for :s1:
+      s1,
+      s2,
+      s3);
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/enumlit_2.vhdl b/testsuite/pyunit/libghdl/examples/comments/enumlit_2.vhdl
new file mode 100644
index 000000000..44aa71d7d
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/enumlit_2.vhdl
@@ -0,0 +1,8 @@
+package p is
+  type state_t is
+    (
+      s1,
+      s2,
+      --  Comment for :s3:
+      s3);
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/enumlit_3.vhdl b/testsuite/pyunit/libghdl/examples/comments/enumlit_3.vhdl
new file mode 100644
index 000000000..7f325f549
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/enumlit_3.vhdl
@@ -0,0 +1,8 @@
+package p is
+  type state_t is
+    (
+      s1,  --  For :s1:
+      s2,
+      s3  --  For :s3:
+      );
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/enumlit_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/enumlit_fail.vhdl
new file mode 100644
index 000000000..36a200402
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/enumlit_fail.vhdl
@@ -0,0 +1,8 @@
+package p is
+  type state_t is
+    (
+      --  Comment
+      s1,
+      s2,
+      s3);
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/func.vhdl b/testsuite/pyunit/libghdl/examples/comments/func.vhdl
new file mode 100644
index 000000000..1c6fc8741
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/func.vhdl
@@ -0,0 +1,6 @@
+package p is
+  -- :log2: as functions are longer in definitions, it might be written before
+  function log2(param : positive) return natural;
+end p;
+
+
diff --git a/testsuite/pyunit/libghdl/examples/comments/func_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/func_fail.vhdl
new file mode 100644
index 000000000..68ff2b80e
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/func_fail.vhdl
@@ -0,0 +1,6 @@
+package p is
+  -- as functions are longer in definitions, it might be written before
+  function log2(param : positive) return natural;
+end p;
+
+
diff --git a/testsuite/pyunit/libghdl/examples/comments/func_param.vhdl b/testsuite/pyunit/libghdl/examples/comments/func_param.vhdl
new file mode 100644
index 000000000..fb47687e5
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/func_param.vhdl
@@ -0,0 +1,9 @@
+package p is
+  function log2(
+    -- :param1: we also want to document parameters too
+    param1 : integer;
+    param2 : boolean
+    ) return natural;
+end p;
+
+
diff --git a/testsuite/pyunit/libghdl/examples/comments/func_param_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/func_param_fail.vhdl
new file mode 100644
index 000000000..53461fdd9
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/func_param_fail.vhdl
@@ -0,0 +1,9 @@
+package p is
+  function log2(
+    -- we also want to document parameters too
+    param1 : integer;
+    param2 : boolean
+    ) return natural;
+end p;
+
+
diff --git a/testsuite/pyunit/libghdl/examples/comments/line1.vhdl b/testsuite/pyunit/libghdl/examples/comments/line1.vhdl
new file mode 100644
index 000000000..2a4ed11bc
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/line1.vhdl
@@ -0,0 +1,4 @@
+architecture arch of ent is
+  signal b1 : bit;  --  Comment for :b1:
+begin
+end arch;
diff --git a/testsuite/pyunit/libghdl/examples/comments/multi1.vhdl b/testsuite/pyunit/libghdl/examples/comments/multi1.vhdl
new file mode 100644
index 000000000..73eebd5b5
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/multi1.vhdl
@@ -0,0 +1,10 @@
+architecture arch of ent is
+  --  Comment for :arch:
+  --  Again for :arch:
+
+  --  Also for :arch:
+
+  --  But for :b1:
+  signal b1 : bit;
+begin
+end arch;
diff --git a/testsuite/pyunit/libghdl/examples/comments/pkg_bef.vhdl b/testsuite/pyunit/libghdl/examples/comments/pkg_bef.vhdl
new file mode 100644
index 000000000..1ed150346
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/pkg_bef.vhdl
@@ -0,0 +1,4 @@
+-- comments before design units :p1:
+-- :p1: might be multiline
+package p1 is
+end package;
diff --git a/testsuite/pyunit/libghdl/examples/comments/pkg_inside.vhdl b/testsuite/pyunit/libghdl/examples/comments/pkg_inside.vhdl
new file mode 100644
index 000000000..c9f6129d4
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/pkg_inside.vhdl
@@ -0,0 +1,5 @@
+-- As packages define public elements like constants, types and sub-programs, we are intrested in such documentation too.:p2:
+package p2 is
+  -- comments in design units (python doc-string style):p2:
+    -- might be multi line :p2:
+end package;
diff --git a/testsuite/pyunit/libghdl/examples/comments/pkg_inside_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/pkg_inside_fail.vhdl
new file mode 100644
index 000000000..4b2b9e653
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/pkg_inside_fail.vhdl
@@ -0,0 +1,5 @@
+package p2 is
+  -- comments in design units (python doc-string style) :fail:
+
+  constant c : natural := 5;
+end package;
diff --git a/testsuite/pyunit/libghdl/examples/comments/pkg_inside_fail2.vhdl b/testsuite/pyunit/libghdl/examples/comments/pkg_inside_fail2.vhdl
new file mode 100644
index 000000000..f5e347488
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/pkg_inside_fail2.vhdl
@@ -0,0 +1,3 @@
+package p2 is
+  -- comments in design units (python doc-string style) :fail:
+end package;
diff --git a/testsuite/pyunit/libghdl/examples/comments/process.vhdl b/testsuite/pyunit/libghdl/examples/comments/process.vhdl
new file mode 100644
index 000000000..c0b56fe6e
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/process.vhdl
@@ -0,0 +1,9 @@
+architecture arch of e is
+  signal s, s_n : bit;
+begin
+  --  Comment for :p:
+  p : process (s)
+  begin
+    s <= not s_n;
+  end process;
+end arch;
diff --git a/testsuite/pyunit/libghdl/examples/comments/process_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/process_fail.vhdl
new file mode 100644
index 000000000..819e5ea6e
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/process_fail.vhdl
@@ -0,0 +1,9 @@
+architecture arch of e is
+  signal s, s_n : bit;
+begin
+  --  Comment
+  p : process (s)
+  begin
+    s <= not s_n;
+  end process;
+end arch;
diff --git a/testsuite/pyunit/libghdl/examples/comments/record.vhdl b/testsuite/pyunit/libghdl/examples/comments/record.vhdl
new file mode 100644
index 000000000..82d5c1faa
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/record.vhdl
@@ -0,0 +1,7 @@
+package p is
+  --  Comment for :rec:
+  type rec is record
+    a : bit;
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/record_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/record_fail.vhdl
new file mode 100644
index 000000000..6288920f7
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/record_fail.vhdl
@@ -0,0 +1,7 @@
+package p is
+  --  Comment for the record
+  type rec is record
+    a : bit;
+    b : bit;
+  end record;
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/sig.vhdl b/testsuite/pyunit/libghdl/examples/comments/sig.vhdl
new file mode 100644
index 000000000..ee0865ae4
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/sig.vhdl
@@ -0,0 +1,5 @@
+architecture arch of ent is
+  --  Comment for :b2:
+  signal b2 : bit;
+begin
+end arch;
diff --git a/testsuite/pyunit/libghdl/examples/comments/sig_2.vhdl b/testsuite/pyunit/libghdl/examples/comments/sig_2.vhdl
new file mode 100644
index 000000000..c825a41e5
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/sig_2.vhdl
@@ -0,0 +1,6 @@
+architecture arch of ent is
+  signal s1 : bit;  --  comment for :s1:
+  --  Also for :s1:
+  signal s2: natural;
+begin
+end arch;
diff --git a/testsuite/pyunit/libghdl/examples/comments/sig_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/sig_fail.vhdl
new file mode 100644
index 000000000..4630d2877
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/sig_fail.vhdl
@@ -0,0 +1,5 @@
+architecture arch of ent is
+  --  Comment
+  signal b2 : bit;
+begin
+end arch;
diff --git a/testsuite/pyunit/libghdl/examples/comments/type.vhdl b/testsuite/pyunit/libghdl/examples/comments/type.vhdl
new file mode 100644
index 000000000..94818ee88
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/type.vhdl
@@ -0,0 +1,4 @@
+package p is
+  --  Comment for :vec:
+  type vec is array(natural range <>) of bit_vector(0 to 1);
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/type_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/type_fail.vhdl
new file mode 100644
index 000000000..bb4050103
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/type_fail.vhdl
@@ -0,0 +1,4 @@
+package p is
+  --  Comment
+  type vec is array(natural range <>) of bit_vector(0 to 1);
+end p;
diff --git a/testsuite/pyunit/libghdl/examples/comments/var.vhdl b/testsuite/pyunit/libghdl/examples/comments/var.vhdl
new file mode 100644
index 000000000..9be81044f
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/var.vhdl
@@ -0,0 +1,12 @@
+architecture arch of ent is
+begin
+  process
+    --  Comment for :v:
+    variable v : natural;
+  begin
+    while v < 10 loop
+      v := v + 1;
+    end loop;
+    wait;
+  end process;
+end arch;
diff --git a/testsuite/pyunit/libghdl/examples/comments/var_fail.vhdl b/testsuite/pyunit/libghdl/examples/comments/var_fail.vhdl
new file mode 100644
index 000000000..71689ff59
--- /dev/null
+++ b/testsuite/pyunit/libghdl/examples/comments/var_fail.vhdl
@@ -0,0 +1,12 @@
+architecture arch of ent is
+begin
+  process
+    --  Comment
+    variable v : natural;
+  begin
+    while v < 10 loop
+      v := v + 1;
+    end loop;
+    wait;
+  end process;
+end arch;