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authorTristan Gingold <tgingold@free.fr>2022-11-27 08:27:19 +0100
committerTristan Gingold <tgingold@free.fr>2022-11-27 12:30:41 +0100
commitad92a80324101d8c85b19d86b08297765df42ef4 (patch)
tree1d3178e2d616b54283b4a2224b6b2cdbeca06f66 /testsuite/pyunit/libghdl/sig_fail.vhdl
parent55e669e57725017cb356907abcfe7a4953563296 (diff)
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testsuite/pyunit/libghdl: remove work-arounds in the tests
Diffstat (limited to 'testsuite/pyunit/libghdl/sig_fail.vhdl')
-rw-r--r--testsuite/pyunit/libghdl/sig_fail.vhdl2
1 files changed, 0 insertions, 2 deletions
diff --git a/testsuite/pyunit/libghdl/sig_fail.vhdl b/testsuite/pyunit/libghdl/sig_fail.vhdl
index c686ef2a5..4630d2877 100644
--- a/testsuite/pyunit/libghdl/sig_fail.vhdl
+++ b/testsuite/pyunit/libghdl/sig_fail.vhdl
@@ -1,6 +1,4 @@
architecture arch of ent is
- signal b1 : bit;
-
-- Comment
signal b2 : bit;
begin