diff options
author | Tristan Gingold <tgingold@free.fr> | 2022-06-26 06:46:59 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2022-06-26 06:46:59 +0200 |
commit | ff90d0d0a59fd84d310c61d25fead5ff94c8aed7 (patch) | |
tree | 9d5c0467d13c992ad3eca9a9d430dea9bcba0dfb /testsuite/pyunit/lsp/010ls28/adder.vhdl | |
parent | 6f24a701e13f81e1f788cc2695a885c7d2ccd22a (diff) | |
download | ghdl-ff90d0d0a59fd84d310c61d25fead5ff94c8aed7.tar.gz ghdl-ff90d0d0a59fd84d310c61d25fead5ff94c8aed7.tar.bz2 ghdl-ff90d0d0a59fd84d310c61d25fead5ff94c8aed7.zip |
testsuite/pyunit/lsp: add a test for ghdl/ghdl-language-server#28
Diffstat (limited to 'testsuite/pyunit/lsp/010ls28/adder.vhdl')
-rw-r--r-- | testsuite/pyunit/lsp/010ls28/adder.vhdl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/pyunit/lsp/010ls28/adder.vhdl b/testsuite/pyunit/lsp/010ls28/adder.vhdl new file mode 100644 index 000000000..2b4e6d887 --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/adder.vhdl @@ -0,0 +1,20 @@ + library ieee; + use ieee.std_logic_1164.all; + + entity adder is + port( + a : in std_logic; + b : in std_logic; + o : out std_logic; + c : out std_logic + ); + end entity; + + architecture comb of adder is + + begin + + o <= a xor b; + c <= a and b; + + end; |