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author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2020-12-28 11:57:02 +0100 |
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committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2020-12-28 11:57:02 +0100 |
commit | 713389ad5d939b8342da0119804a3dfeeb8c49de (patch) | |
tree | f107400f8a5ccb9e0742d4a2fb811e732664c7b8 /testsuite/pyunit | |
parent | 12f8c883dee453c5bfc318334b0d43f952aeed18 (diff) | |
download | ghdl-713389ad5d939b8342da0119804a3dfeeb8c49de.tar.gz ghdl-713389ad5d939b8342da0119804a3dfeeb8c49de.tar.bz2 ghdl-713389ad5d939b8342da0119804a3dfeeb8c49de.zip |
Translatest `python/units01` test to a unit test in Python.
Diffstat (limited to 'testsuite/pyunit')
-rw-r--r-- | testsuite/pyunit/libghdl/Initialize.py | 77 | ||||
-rw-r--r-- | testsuite/pyunit/libghdl/simpleEntity.vhdl | 26 |
2 files changed, 95 insertions, 8 deletions
diff --git a/testsuite/pyunit/libghdl/Initialize.py b/testsuite/pyunit/libghdl/Initialize.py index b7e370650..7392f1efc 100644 --- a/testsuite/pyunit/libghdl/Initialize.py +++ b/testsuite/pyunit/libghdl/Initialize.py @@ -1,20 +1,81 @@ +from pathlib import Path +from typing import Any, NoReturn from unittest import TestCase +import libghdl +from libghdl.thin import name_table +from libghdl.thin import files_map +from libghdl.thin.vhdl import nodes +from libghdl.thin.vhdl import sem_lib +from libghdl.thin import errorout_console + if __name__ == "__main__": print("ERROR: you called a testcase declaration file as an executable module.") print("Use: 'python -m unitest <testcase module>'") exit(1) + class Instantiate(TestCase): - def test_InitializeGHDL(self): - pass + _filename : Path = Path("simpleEntity.vhdl") + _sfe: Any + _file: Any + + _continueTesting = True + + @staticmethod + def getIdentifier(node): + """Return the Python string from node :param:`node` identifier""" + return name_table.Get_Name_Ptr(nodes.Get_Identifier(node)).decode("utf-8") + + def setUp(self) -> None: + """Check for every test, if tests should continue.""" + if not self.__class__._continueTesting: + self.skipTest("No reason to go on.") + + def fail(self, msg: Any = ...) -> NoReturn: + self.__class__._continueTesting = False + super().fail(msg) + + def test_InitializeGHDL(self) -> None: + """Initialization: set options and then load libaries""" + + # Print error messages on the console. + errorout_console.Install_Handler() + + # Set options. This must be done before analyze_init() + libghdl.set_option(b"--std=08") + + # Finish initialization. This will load the standard package. + if libghdl.analyze_init_status() != 0: + self.fail("libghdl initialization error") + + def test_ReadSourceFile(self) -> None: + # Load the file + file_id = name_table.Get_Identifier(str(self._filename).encode("utf_8")) + self._sfe = files_map.Read_Source_File(name_table.Null_Identifier, file_id) + if self._sfe == files_map.No_Source_File_Entry: + self.fail("Cannot read file '{!s}'".format(self._filename)) + + def test_ParseFile(self) -> None: + # Parse + self._file = sem_lib.Load_File(self._sfe) + + def test_ListDesignUnits_WhileLoop(self) -> None: + # Display all design units + designUnit = nodes.Get_First_Design_Unit(self._file) + while designUnit != nodes.Null_Iir: + libraryUnit = nodes.Get_Library_Unit(designUnit) + + if nodes.Get_Kind(libraryUnit) == nodes.Iir_Kind.Entity_Declaration: + entityName = self.getIdentifier(libraryUnit) + self.assertTrue(entityName == "e1") - def test_ReadSourceFile(self): - pass + elif nodes.Get_Kind(libraryUnit) == nodes.Iir_Kind.Architecture_Body: + architectureName = self.getIdentifier(libraryUnit) + self.assertTrue(architectureName == "arch") - def test_ParseFile(self): - pass + else: + self.fail("Unknown unit.") - def test_ListDesignUnits(self): - pass + designUnit = nodes.Get_Chain(designUnit) diff --git a/testsuite/pyunit/libghdl/simpleEntity.vhdl b/testsuite/pyunit/libghdl/simpleEntity.vhdl new file mode 100644 index 000000000..bfcb0aceb --- /dev/null +++ b/testsuite/pyunit/libghdl/simpleEntity.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.numeric_std.all; + +entity e1 is + generic ( + BITS : positive = 8 + port ( + Clock: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(BITS - 1 downto 0) + ); +end entity e1; + +architecture behav of e1 is +begin + process(Clock) + begin + if rising_edge(Clock) then + if Reset = '1' then + Q <= (others => '0'); + else + Q <= std_logic_vector(unsigned(Q) + 1); + end if; + end if; + end process; +end architecture behav; |