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authorPatrick Lehmann <Patrick.Lehmann@plc2.de>2021-06-28 17:24:40 +0200
committerPatrick Lehmann <Patrick.Lehmann@plc2.de>2021-07-01 06:39:46 +0200
commite8556a64e6ad3cedbe4862e6be992f516536abf7 (patch)
tree5f5f7f3cd8cc0522742488c7060f014d92a2e5b6 /testsuite/pyunit
parent3c26dd63f093e156c9bf4143aeddafd3a4664ecc (diff)
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Rework and fine tuning.
Diffstat (limited to 'testsuite/pyunit')
-rw-r--r--testsuite/pyunit/Current.vhdl13
-rw-r--r--testsuite/pyunit/dom/Expressions.py6
2 files changed, 12 insertions, 7 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index a017b9f46..4ac967c15 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -5,12 +5,14 @@ use ieee.numeric_std.all;
entity entity_1 is
generic (
FREQ : real := 100.0;
- BITS : positive := 8
+ BITS : positive := 8.5 ns;
+ type Typ
);
port (
- Clock: in std_logic;
+ Clock: in std_logic := 5 ns;
Reset: in std_logic := '0';
- Q: out std_logic_vector(BITS - 1 downto 0)
+ D: inout bit_vector(clock'range);
+ Q: out std_logic_vector(BITS'left - 1 downto Re.set)
);
constant fire : boolean := True;
@@ -20,6 +22,7 @@ end entity entity_1;
architecture behav of entity_1 is
constant MAX : positive := -25;
+
signal rst : std_logic := foo('U');
signal vec : bit_vector(pack(3 to 2).signaal'range'value);
signal copy : input'subtype;
@@ -94,8 +97,10 @@ package package_1 is
use lib.pack.all;
+ type cell;
+
constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10); -- 2.3;
- attribute fixed of ghdl : constant is true;
+ attribute fixed of ghdl [bar] : constant is true;
component comp is
port (
diff --git a/testsuite/pyunit/dom/Expressions.py b/testsuite/pyunit/dom/Expressions.py
index 4de36a2b2..6f64c6c86 100644
--- a/testsuite/pyunit/dom/Expressions.py
+++ b/testsuite/pyunit/dom/Expressions.py
@@ -87,9 +87,9 @@ class Expressions(TestCase):
default: Expression = self.parse(filename, constantDeclartion)
# Start checks
- self.assertTrue(isinstance(default, InverseExpression))
- self.assertTrue(isinstance(default.Operand, SimpleObjectOrFunctionCallSymbol))
- self.assertTrue(default.Operand.SymbolName == "true")
+ self.assertIsInstance(default, InverseExpression)
+ self.assertIsInstance(default.Operand, SimpleObjectOrFunctionCallSymbol)
+ self.assertTrue(str(default.Operand.SymbolName) == "true")
# def test_AbsExpression(self):
# filename: Path = self._root / "{className}_{funcName}.vhdl".format(