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authorTristan Gingold <tgingold@free.fr>2019-07-20 10:22:07 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-20 10:22:07 +0200
commit817670af605bad21b3a872cb14b8d04b85b2d466 (patch)
tree56fbdc45c2bc784272daa0119abb60fde7189373 /testsuite/synth/aggr01/tb_aggr01.vhdl
parentec253b52f8b49815221c03cf55cc7a991d981c61 (diff)
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synth: add a test for previous commit (aggr).
Diffstat (limited to 'testsuite/synth/aggr01/tb_aggr01.vhdl')
-rw-r--r--testsuite/synth/aggr01/tb_aggr01.vhdl25
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/aggr01/tb_aggr01.vhdl b/testsuite/synth/aggr01/tb_aggr01.vhdl
new file mode 100644
index 000000000..429117cc9
--- /dev/null
+++ b/testsuite/synth/aggr01/tb_aggr01.vhdl
@@ -0,0 +1,25 @@
+entity tb_aggr01 is
+end tb_aggr01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_aggr01 is
+ signal a, b : std_logic_vector(7 downto 0);
+begin
+ dut: entity work.aggr01
+ port map (a, b);
+
+ process
+ begin
+ a <= x"ff";
+ wait for 1 ns;
+ assert b = x"01" severity failure;
+
+ a <= x"ee";
+ wait for 1 ns;
+ assert b = x"00" severity failure;
+
+ wait;
+ end process;
+end behav;