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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-08 05:24:04 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-08 05:24:04 +0200 |
| commit | 1a0606c144230040143e8080016302bc51a48bfb (patch) | |
| tree | 41298609c1d76fb9dff8c82e8caa9aa4535ef9b7 /testsuite/synth/aggr02/targ01.vhdl | |
| parent | 16eb29c7ca5928517d7a49c77deae6d1f6c9437b (diff) | |
| download | ghdl-1a0606c144230040143e8080016302bc51a48bfb.tar.gz ghdl-1a0606c144230040143e8080016302bc51a48bfb.tar.bz2 ghdl-1a0606c144230040143e8080016302bc51a48bfb.zip | |
synth: add testcase for aggregate target.
Diffstat (limited to 'testsuite/synth/aggr02/targ01.vhdl')
| -rw-r--r-- | testsuite/synth/aggr02/targ01.vhdl | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/testsuite/synth/aggr02/targ01.vhdl b/testsuite/synth/aggr02/targ01.vhdl new file mode 100644 index 000000000..f794fc8dc --- /dev/null +++ b/testsuite/synth/aggr02/targ01.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity targ01 is + port (v : std_logic_vector (2 downto 0); + o0, o1, o2 : out std_logic); +end targ01; + +architecture behav of targ01 is +begin + (o2, o1, o0) <= v; +end behav; |