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authorTristan Gingold <tgingold@free.fr>2019-10-02 18:38:24 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-02 18:38:24 +0200
commitbfad2a487e2e6f6476e9417d70dff73656041883 (patch)
treefa158658cb2d35ab588dfe0b2aa99e00ce99712f /testsuite/synth/asgn01/asgn07.vhdl
parent8b212a75204bd4bc6cc7cca583377fdf86651f2a (diff)
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testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/asgn01/asgn07.vhdl')
-rw-r--r--testsuite/synth/asgn01/asgn07.vhdl26
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/asgn01/asgn07.vhdl b/testsuite/synth/asgn01/asgn07.vhdl
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+++ b/testsuite/synth/asgn01/asgn07.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity asgn07 is
+ port (clk : std_logic;
+ s0 : std_logic;
+ r : out std_logic_vector (65 downto 0));
+end asgn07;
+
+architecture behav of asgn07 is
+begin
+ process (clk) is
+ begin
+ if rising_edge(clk) then
+ if s0 = '1' then
+ r (0) <= '1';
+ r (64 downto 1) <= x"ffff_eeee_dddd_cccc";
+ r (65) <= '1';
+ else
+ r (0) <= '0';
+ r (8 downto 5) <= x"7";
+ r (65) <= '0';
+ end if;
+ end if;
+ end process;
+end behav;