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author | Tristan Gingold <tgingold@free.fr> | 2019-08-27 13:40:48 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-08-27 13:40:57 +0200 |
commit | 26c13e748d27454a43ea1c341570b48a40cd2067 (patch) | |
tree | 0e04e88f170011443255aa97bd476afce9a73fca /testsuite/synth/asgn01/tb_asgn02.vhdl | |
parent | ef26f6ae06c01187403be345f5997930cbd44a10 (diff) | |
download | ghdl-26c13e748d27454a43ea1c341570b48a40cd2067.tar.gz ghdl-26c13e748d27454a43ea1c341570b48a40cd2067.tar.bz2 ghdl-26c13e748d27454a43ea1c341570b48a40cd2067.zip |
testsuite/synth: add cases for assign.
Diffstat (limited to 'testsuite/synth/asgn01/tb_asgn02.vhdl')
-rw-r--r-- | testsuite/synth/asgn01/tb_asgn02.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/asgn01/tb_asgn02.vhdl b/testsuite/synth/asgn01/tb_asgn02.vhdl new file mode 100644 index 000000000..76382a71b --- /dev/null +++ b/testsuite/synth/asgn01/tb_asgn02.vhdl @@ -0,0 +1,26 @@ +entity tb_asgn02 is +end tb_asgn02; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_asgn02 is + signal s0 : std_logic; + signal r : std_logic_vector (2 downto 0); +begin + dut: entity work.asgn02 + port map (s0 => s0, r => r); + + process + begin + s0 <= '1'; + wait for 1 ns; + assert r = "010" severity failure; + + s0 <= '0'; + wait for 1 ns; + assert r = "000" severity failure; + + wait; + end process; +end behav; |