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authorTristan Gingold <tgingold@free.fr>2019-08-31 05:48:05 +0200
committerTristan Gingold <tgingold@free.fr>2019-08-31 06:25:52 +0200
commita14e0e60f448526f6ee4dc2bb2a524a8cd324f6f (patch)
tree7c4c011375a2f2851f5cdf25743e279f66e28776 /testsuite/synth/asgn01/tb_asgn03.vhdl
parent88942b924c92f2f90418706718b1bec3d38af007 (diff)
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[PATCH] synth-environment: fix thinkos.
Diffstat (limited to 'testsuite/synth/asgn01/tb_asgn03.vhdl')
-rw-r--r--testsuite/synth/asgn01/tb_asgn03.vhdl39
1 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/synth/asgn01/tb_asgn03.vhdl b/testsuite/synth/asgn01/tb_asgn03.vhdl
new file mode 100644
index 000000000..f4f474c41
--- /dev/null
+++ b/testsuite/synth/asgn01/tb_asgn03.vhdl
@@ -0,0 +1,39 @@
+entity tb_asgn03 is
+end tb_asgn03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_asgn03 is
+ signal s0 : std_logic;
+ signal s1 : std_logic;
+ signal r : std_logic_vector (2 downto 0);
+begin
+ dut: entity work.asgn03
+ port map (s0 => s0, s1 => s1, r => r);
+
+ process
+ begin
+ s0 <= '0';
+ s1 <= '0';
+ wait for 1 ns;
+ assert r = "000" severity failure;
+
+ s0 <= '0';
+ s1 <= '1';
+ wait for 1 ns;
+ assert r = "000" severity failure;
+
+ s0 <= '1';
+ s1 <= '0';
+ wait for 1 ns;
+ assert r = "010" severity failure;
+
+ s0 <= '1';
+ s1 <= '1';
+ wait for 1 ns;
+ assert r = "011" severity failure;
+
+ wait;
+ end process;
+end behav;