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author | Tristan Gingold <tgingold@free.fr> | 2019-09-21 16:37:35 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-21 16:37:35 +0200 |
commit | 27656301fac956c7ca558feac3a5037c368d553b (patch) | |
tree | 53654ffb20dd615eecc6a54a2ca94c23a4f82980 /testsuite/synth/bug01/display2.vhdl | |
parent | 06d92830364fe1115d32a120d6e531cc498eb5b2 (diff) | |
download | ghdl-27656301fac956c7ca558feac3a5037c368d553b.tar.gz ghdl-27656301fac956c7ca558feac3a5037c368d553b.tar.bz2 ghdl-27656301fac956c7ca558feac3a5037c368d553b.zip |
testsuite/synth: add testcase for previous commit.
Diffstat (limited to 'testsuite/synth/bug01/display2.vhdl')
-rw-r--r-- | testsuite/synth/bug01/display2.vhdl | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/testsuite/synth/bug01/display2.vhdl b/testsuite/synth/bug01/display2.vhdl new file mode 100644 index 000000000..8d7462c24 --- /dev/null +++ b/testsuite/synth/bug01/display2.vhdl @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity display is + port ( + clk : in std_logic; + rst_n : in std_logic; + twochars : in std_logic_vector(15 downto 0) + ); +end display; + +architecture behavior of display is + signal disp_ena : std_logic; + signal column : integer; + signal row : integer; + signal col2x : unsigned(9 downto 0); + signal row2x : unsigned(9 downto 0); + signal ucol : unsigned(9 downto 0); + signal urow : unsigned(9 downto 0); + signal tileaddress : std_logic_vector(10 downto 0); + signal char : std_logic_vector(7 downto 0); + signal char_row : std_logic_vector(7 downto 0); + +begin + + -- 8x8 bitmap is upscaled 2x + ucol <= to_unsigned(column, 10); + urow <= to_unsigned(row, 10); + col2x <= shift_right(urow, 1); + row2x <= shift_right(ucol, 1); + + +end; + |