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author | Tristan Gingold <tgingold@free.fr> | 2019-11-12 20:07:15 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-12 20:36:03 +0100 |
commit | b4490abb58f7a4d1f13900bd3a6c39f64d4dab7f (patch) | |
tree | 28497a3876fcc4503fbedb5834be6dfe28a074fd /testsuite/synth/bug02/repro2.vhdl | |
parent | 97c875c15734f991e1c7b190385def8f0b587538 (diff) | |
download | ghdl-b4490abb58f7a4d1f13900bd3a6c39f64d4dab7f.tar.gz ghdl-b4490abb58f7a4d1f13900bd3a6c39f64d4dab7f.tar.bz2 ghdl-b4490abb58f7a4d1f13900bd3a6c39f64d4dab7f.zip |
testsuite/synth: add tests for previous commit.
Diffstat (limited to 'testsuite/synth/bug02/repro2.vhdl')
-rw-r--r-- | testsuite/synth/bug02/repro2.vhdl | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/testsuite/synth/bug02/repro2.vhdl b/testsuite/synth/bug02/repro2.vhdl new file mode 100644 index 000000000..6968e254d --- /dev/null +++ b/testsuite/synth/bug02/repro2.vhdl @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro2 is + port ( + clk_i : in std_logic; + rst_n_i : in std_logic; + vec_i : in std_logic_vector(0 to 0) + ); +end repro2; + +architecture rtl of repro2 is + signal s_sel : natural range vec_i'range; + signal s_true : std_logic; +begin + s_true <= '1'; + + process (clk_i) + begin + if rising_edge(clk_i) then + for i in vec_i'range loop + if s_true = '1' then + s_sel <= i; + exit; + end if; + end loop; + end if; + end process; +end rtl; |