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author | Tristan Gingold <tgingold@free.fr> | 2019-07-24 08:30:07 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-24 08:30:07 +0200 |
commit | a458b0b9bde7d3152adf9b78c5d0a56c5d45915f (patch) | |
tree | 6d0a7ad590764a559ea70a389ffccb8f5d8d08c3 /testsuite/synth/case01/case02.vhdl | |
parent | 121b6579b633d814e27980e1c48c46582276885e (diff) | |
download | ghdl-a458b0b9bde7d3152adf9b78c5d0a56c5d45915f.tar.gz ghdl-a458b0b9bde7d3152adf9b78c5d0a56c5d45915f.tar.bz2 ghdl-a458b0b9bde7d3152adf9b78c5d0a56c5d45915f.zip |
synth: add testcase for previous commit.
Diffstat (limited to 'testsuite/synth/case01/case02.vhdl')
-rw-r--r-- | testsuite/synth/case01/case02.vhdl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/synth/case01/case02.vhdl b/testsuite/synth/case01/case02.vhdl new file mode 100644 index 000000000..3c1b08cbd --- /dev/null +++ b/testsuite/synth/case01/case02.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity case02 is + port (a : std_logic_vector (4 downto 0); + o : out std_logic); +end case02; + +architecture behav of case02 is +begin + with a select o <= + '1' when "00011", + '1' when "00110" | "00111" | "10001", + '0' when "00100", + '1' when "01100", + '1' when "10000", + '0' when others; +end behav; |