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authorTristan Gingold <tgingold@free.fr>2019-07-24 08:30:07 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-24 08:30:07 +0200
commita458b0b9bde7d3152adf9b78c5d0a56c5d45915f (patch)
tree6d0a7ad590764a559ea70a389ffccb8f5d8d08c3 /testsuite/synth/case01/case02.vhdl
parent121b6579b633d814e27980e1c48c46582276885e (diff)
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synth: add testcase for previous commit.
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diff --git a/testsuite/synth/case01/case02.vhdl b/testsuite/synth/case01/case02.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity case02 is
+ port (a : std_logic_vector (4 downto 0);
+ o : out std_logic);
+end case02;
+
+architecture behav of case02 is
+begin
+ with a select o <=
+ '1' when "00011",
+ '1' when "00110" | "00111" | "10001",
+ '0' when "00100",
+ '1' when "01100",
+ '1' when "10000",
+ '0' when others;
+end behav;