diff options
author | Tristan Gingold <tgingold@free.fr> | 2020-05-09 11:02:23 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2020-05-09 11:22:01 +0200 |
commit | 1a65ac6bbbaf6cdaf1ea93c0c46f2e97e12e9dcc (patch) | |
tree | 13d03fcaf314a19649f4ed1c750d8f01678a027e /testsuite/synth/case01/case04.vhdl | |
parent | b13b9e9fa26121a68d74589ef35ea5ed45316cd9 (diff) | |
download | ghdl-1a65ac6bbbaf6cdaf1ea93c0c46f2e97e12e9dcc.tar.gz ghdl-1a65ac6bbbaf6cdaf1ea93c0c46f2e97e12e9dcc.tar.bz2 ghdl-1a65ac6bbbaf6cdaf1ea93c0c46f2e97e12e9dcc.zip |
testsuite/synth: add case tests for corner case.
Diffstat (limited to 'testsuite/synth/case01/case04.vhdl')
-rw-r--r-- | testsuite/synth/case01/case04.vhdl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/synth/case01/case04.vhdl b/testsuite/synth/case01/case04.vhdl new file mode 100644 index 000000000..cf90e85ed --- /dev/null +++ b/testsuite/synth/case01/case04.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity case04 is + port (a : std_logic_vector (4 downto 0); + o : out std_logic); +end case04; + +architecture behav of case04 is +begin + process (a) + begin + o <= '0'; + case a is + when others => + o <= '1'; + end case; + end process; +end behav; |