synth: add a simple test for instantiation.

1 files changed, 12 insertions, 0 deletions

diff --git a/testsuite/synth/comp01/and3.vhdl b/testsuite/synth/comp01/and3.vhdl
new file mode 100644
index 000000000..be0a0c821
--- /dev/null
+++ b/testsuite/synth/comp01/and3.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity and3 is
+  port (a, b, c : std_logic;
+        o : out std_logic);
+end and3;
+
+architecture behav of and3 is
+begin
+  o <= a and b and c;
+end behav;