synth: add a simple test for instantiation.

1 files changed, 21 insertions, 0 deletions

diff --git a/testsuite/synth/comp01/and6comp.vhdl b/testsuite/synth/comp01/and6comp.vhdl
new file mode 100644
index 000000000..8cdb8f821
--- /dev/null
+++ b/testsuite/synth/comp01/and6comp.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity and6comp is
+  port (i0, i1, i2, i3, i4, i5 : std_logic;
+        o : out std_logic);
+end and6comp;
+
+architecture behav of and6comp is
+  component and3 is
+    port (a, b, c : std_logic;
+          o : out std_logic);
+  end component;
+  signal t1, t2 : std_logic;
+begin
+  a1: and3
+    port map (i0, i1, i2, t1);
+  a2: and3
+    port map (i3, i4, i5, t2);
+  o <= t1 and t2;
+end behav;