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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-29 11:37:35 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-29 11:37:35 +0200 |
| commit | 4d71e55689449b49b6732e26a34469188564f8b4 (patch) | |
| tree | 0e24456ef5086a1fea2945894a69cb0998209cfd /testsuite/synth/dff01/dff04.vhdl | |
| parent | 5fc2b23c0a27e281d3c1f1927379aa1fd9300df0 (diff) | |
| download | ghdl-4d71e55689449b49b6732e26a34469188564f8b4.tar.gz ghdl-4d71e55689449b49b6732e26a34469188564f8b4.tar.bz2 ghdl-4d71e55689449b49b6732e26a34469188564f8b4.zip | |
testsuite/synth/dff01: add testbenches.
Diffstat (limited to 'testsuite/synth/dff01/dff04.vhdl')
| -rw-r--r-- | testsuite/synth/dff01/dff04.vhdl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/synth/dff01/dff04.vhdl b/testsuite/synth/dff01/dff04.vhdl index 9e7e60478..29ea5fee0 100644 --- a/testsuite/synth/dff01/dff04.vhdl +++ b/testsuite/synth/dff01/dff04.vhdl @@ -11,7 +11,7 @@ end dff04; architecture behav of dff04 is signal q : std_logic_vector(7 downto 0); begin - process (clk) is + process (clk, q) is begin if rising_edge (clk) then q <= d; |