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author | Tristan Gingold <tgingold@free.fr> | 2019-10-14 20:54:09 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-14 20:54:09 +0200 |
commit | 987b58addadbef067a3dca4e3c687f098e0b265a (patch) | |
tree | d121bbccc9921b336431ebeca5938b7cac5514a2 /testsuite/synth/dff03/dff04.vhdl | |
parent | 02dc85ef9b2179ffe15d0c8172e44786a2216d39 (diff) | |
download | ghdl-987b58addadbef067a3dca4e3c687f098e0b265a.tar.gz ghdl-987b58addadbef067a3dca4e3c687f098e0b265a.tar.bz2 ghdl-987b58addadbef067a3dca4e3c687f098e0b265a.zip |
testsuite/synth: add testcases for previous commit.
Diffstat (limited to 'testsuite/synth/dff03/dff04.vhdl')
-rw-r--r-- | testsuite/synth/dff03/dff04.vhdl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/synth/dff03/dff04.vhdl b/testsuite/synth/dff03/dff04.vhdl new file mode 100644 index 000000000..58d1f9b32 --- /dev/null +++ b/testsuite/synth/dff03/dff04.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff04 is + port (q : out std_logic; + d : std_logic; + en1 : std_logic; + en2 : std_logic; + clk : std_logic); +end dff04; + +architecture behav of dff04 is +begin + process (clk) is + begin + if en2 = '1' and (rising_edge (clk) and en1 = '1') then + q <= d; + end if; + end process; +end behav; |