aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite/synth/dispin01/rec03.vhdl
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2019-09-04 06:52:35 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-04 06:52:35 +0200
commit4cb565baea6e93f804bef253200f0872428a3daa (patch)
tree6ed5ee76fe6c1c9e52d94a03666e1d121ccfd094 /testsuite/synth/dispin01/rec03.vhdl
parent95433bc986b16badf5a48ab00df861d0424ca983 (diff)
downloadghdl-4cb565baea6e93f804bef253200f0872428a3daa.tar.gz
ghdl-4cb565baea6e93f804bef253200f0872428a3daa.tar.bz2
ghdl-4cb565baea6e93f804bef253200f0872428a3daa.zip
testsuite/synth: rename disp01 to dispin01
Diffstat (limited to 'testsuite/synth/dispin01/rec03.vhdl')
-rw-r--r--testsuite/synth/dispin01/rec03.vhdl13
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/synth/dispin01/rec03.vhdl b/testsuite/synth/dispin01/rec03.vhdl
new file mode 100644
index 000000000..f50e5eb09
--- /dev/null
+++ b/testsuite/synth/dispin01/rec03.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec03_pkg.all;
+
+entity rec03 is
+ port (inp : myrec;
+ o : out std_logic);
+end rec03;
+
+architecture behav of rec03 is
+begin
+ o <= inp.b when inp.a = s2 else '1';
+end behav;